LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 15

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADD
0x13
0x14
0x15
Name
Alignment Control –
TOF3
Alignment Control –
AFS
Loss of Alignment
Control
Bits
7:6
5:4
3:1
0
7:6
5:4
3
2:1
0
7:3
2:0
Field
RSVD
TOF3_Align_Mode
RSVD
TOF3_INIT
RSVD
AFS_Align_Mode
AFS_Init_Input
RSVD
AFS_INIT
RSVD
LOA_Window
15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
11
0
11
0
0
010
Description
Reserved
00 = auto align when misaligned
01 = one shot manual align when writing
TOF3_INIT=1
10 = always align
11= never align
Reserved
Writing one to this bit while also writing
TOF3_Align_Mode
TOF3_INIT output to go high for at least one
vframe period + one Hsync period and not
more than one vframe period + two Hsync
periods. The assertion of TOF3_init must
happen immediately (it cannot wait for
Hsync). If TOF3_Align_Mode is being written
to 3, this bit will have no effect. This bit is self-
clearing and will always read zero.
Reserved
00 = auto align when misaligned
01 = one shot manual align. AFS_Init_Input
reg determines if done by pin (INIT) or
register (AFS_INIT = 1)
10 = always align
11= never align
0 = Rising edges on INIT (pin 6) trigger AFS
one shot manual align.
1 = Writing ‘1’ to AFS_Init register triggers
AFS one shot manual align.
Reserved
Writing one to this bit while also writing
AFS_Align_Mode = 3 and AFS_Init_Input=1,
or providing a rising edge on the init input
when AFS_Align_Mode
AFS_Init_Input=0, will cause the AFS_INIT
output to go high for at least one vframe
period + one Hsync period and not more than
one vframe period + two Hsync periods. The
assertion of AFS_INIT must happen
immediately (it cannot wait for Hsync). If
AFS_Align_Mode = 3, toggling the init input
will have no effect.
This bit is self-clearing and will always read
zero.
Reserved
Number of 27 MHz clocks between the TOF1
and Vsync before Loss of Alignment is
reported.
If the code loaded in this register is n, then
Loss of Alignment will be reported if the
difference between TOF1 and Vsync
exceeds 2
n
27 MHz clock cycles
≠
3, will cause the
≠
3 and
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