DS28CN01 Maxim, DS28CN01 Datasheet - Page 7

• Manufacturer Part Number: DS28CN01
• Description: The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications (FIPS) 180-1/180-2 and ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1)
• Manufacturer: Maxim

Figure 3. I
Acknowledged by Slave
A slave device, when addressed, is usually obliged to
generate an acknowledge after the receipt of each
byte. The master must generate the clock pulse for
each acknowledge bit. A slave that acknowledges must
pull down the SDA line during the acknowledge clock
pulse so that it remains stable low during the high peri-
od of this clock pulse. Setup and hold times t
and t
Acknowledged by Master
To continue reading from a slave, the master is obliged
to generate an acknowledge after the receipt of each
byte. The master must generate the clock pulse for
each acknowledge bit. A master that acknowledges
must pull down the SDA line during the acknowledge
clock pulse so that it remains stable low during the high
period of this clock pulse. Setup and hold times t
and t
Not Acknowledged by Slave
A slave device may be unable to receive or transmit
data either because of an invalid access mode,
because the SHA-1 engine is running, or because a
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
HD:DAT
HD:DAT
STOP
2
C/SMBus Timing Diagram
1Kb I
t
BUF
must be taken into account.
must be taken into account.
START
_______________________________________________________________________________________
t
HD:STA
IL(MAX)
2
t
LOW
ABRIDGED DATA SHEET
AND V
C/SMBus EEPROM with SHA-1 Engine
IH(MIN)
t
R
.
t
HD:DAT
t
HIGH
SU:DAT
t
SU:DAT
F
t
SU:DAT
EEPROM write cycle is in progress. In this case, the
DS28CN01 does not acknowledge any bytes that it
refuses by leaving SDA high during the high period of
the acknowledge-related clock pulse. See the Read
and Write section in the full data sheet for a detailed list
of situations where the DS28CN01 does not acknowl-
edge.
Not Acknowledged by Master
At some time when receiving data, the master must ter-
minate a read access. To achieve this, the master does
not acknowledge the last byte that it has received from
the slave by leaving SDA high during the high period of
the acknowledge-related clock pulse. In response, the
slave stops transmitting, allowing the master to gener-
ate a STOP condition.
For this section including Figures 4 and 5 and Table 2,
refer to the full version of the data sheet.
Read and Write
This section discusses the read and write behavior of
the EEPROM and the various registers. Refer to the full
data sheet for details, including Tables 3 to 13.
REPEATED
START
t
SU:STA
t
HD:STA
Data Memory and Registers
t
SP
t
SU:STO
7