DS28CN01 Maxim, DS28CN01 Datasheet - Page 6

• Manufacturer Part Number: DS28CN01
• Description: The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications (FIPS) 180-1/180-2 and ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1)
• Manufacturer: Maxim

1Kb I
Figure 2. I
Data transfers can be initiated only when the bus is not
busy. The master generates the SCL, controls the bus
access, generates the START and STOP conditions,
and determines the number of bytes transferred on the
SDA line between START and STOP. Data is transferred
in bytes with the most significant bit being transmitted
first. After each byte, an acknowledge bit follows to
allow synchronization between master and slave.
During any data transfer, SDA must remain stable
whenever the clock line is high. Changes in the SDA
line while SCL is high are interpreted as a START or a
STOP. The protocol is illustrated in Figure 2. See Figure
3 for detailed timing references.
Bus Idle or Not Busy
Both SDA and SCL are inactive, i.e., in their logic-high
states.
START Condition
To initiate communication with a slave, the master must
generate a START condition. A START condition is
defined as a change in state of SDA from high to low
while SCL remains high.
STOP Condition
To end communication with a slave the master must
generate a STOP condition. A STOP condition is
defined as a change in state of SDA from low to high
while SCL remains high.
6
SDA
SCL
_______________________________________________________________________________________
IDLE
2
C/SMBus Protocol Overview
CONDITION
START
2
C/SMBus EEPROM with SHA-1 Engine
ADDRESS
MSB FIRST
SLAVE
1–7
ABRIDGED DATA SHEET
I
2
C/SMBus Protocol
R/W
8
ACK
9
MSB
1–7
REPEATED IF MORE BYTES
ARE TRANSFERRED
DATA
LSB
Repeated START Condition
Repeated STARTs are commonly used for read access-
es after having specified a memory address to read
from in a preceding write access. The master can use a
repeated START condition at the end of a data transfer
to immediately initiate a new data transfer following the
current one. A repeated START condition is generated
the same way as a normal START condition, but without
a preceding STOP condition.
Data Valid
With the exception of the START and STOP condition,
transitions of SDA can occur only during the low state
of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
required setup and hold time (t
edge of SCL and t
SCL; see Figure 3). There is one clock pulse per bit of
data. Data is shifted into the receiving device during
the rising edge of the SCL pulse.
When finished with writing, the master must release the
SDA line for a sufficient amount of setup time (minimum
t
SCL to start reading. The slave shifts out each data bit
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. The master generates all SCL clock pulses,
including those needed to read from a slave.
8
SU:DAT
ACK
9
+ t
R
in Figure 3) before the next rising edge of
MSB
1–7
SU:DAT
DATA
LSB
8
before the rising edge of
HD:DAT
NACK
ACK/
9
STOP CONDITION
REPEATED START
after the falling