ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 99

• Manufacturer Part Number: ST7260E1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
• Manufacturer: STMicroelectronics

Specifications of ST7260E1

• 4 Or 8 Kbytes Program Memory: high density Flash (HDFlash), or FastROM with readout and write protection

ST7260xx
Note:
Note:
Note:
Table 46.
Address
(Hex.)
2C
2D
2A
2B
25
26
27
28
29
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Register
DADDR
End suspend (ESUSP)
The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7
automatically terminates HALT mode.
Correct transfer (CTR)
1.
Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register,
independently of the endpoint number addressed by the transfer which generated the CTR
interrupt.
If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and
STAT_RX are set to NAK.
2.
When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register and EP1-EP0 bits in
the IDR register stay unchanged until the CTR bit in the ISTR register is cleared.
3.
USB register map and reset values
EP0RA
EP0RB
DMAR
name
CTLR
PIDR
ISTR
IMR
IDR
When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to
NAK.
Read the PIDR to obtain the token and the IDR to get the endpoint number related to
the last transfer.
Clear the CTR bit in the ISTR register.
ST_OUT
SUSPM
SUSP
DA15
DA7
TP3
7
0
0
0
0
0
0
0
1
1
x
x
x
DTOG_RX
DTOG_TX
DOVRM
DOVR
ADD6
DA14
DA6
TP2
6
x
x
x
0
0
0
0
0
0
0
STAT_TX1
STAT_RX
CTRM
ADD5
DA13
CTR
EP1
5
0
0
0
0
0
0
0
0
1
0
x
x
STAT_TX0
STAT_RX
ERRM
ADD4
DA12
ERR
EP0
4
0
0
0
0
0
0
0
0
0
0
x
x
RESUM
IOVRM
CNT3
ADD3
TBC3
DA11
IOVR
E
3
0
0
x
0
0
0
0
0
x
0
0
RX_SEZ
ESUSP
ESUSP
PDWN
ADD2
CNT2
TBC2
DA10
M
2
0
0
0
0
1
0
0
0
x
x
USB interface (USB)
RESET
RESET
FSUSP
ADD1
CNT1
TBC1
RXD
DA9
M
1
0
0
0
0
1
0
0
0
x
x
SOFM
FRES
ADD0
CNT0
TBC0
SOF
DA8
99/139
0
0
0
0
0
0
0
0
0
0
x
x