ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 95

• Manufacturer Part Number: ST7260E1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
• Manufacturer: STMicroelectronics

Specifications of ST7260E1

• 4 Or 8 Kbytes Program Memory: high density Flash (HDFlash), or FastROM with readout and write protection

ST7260xx
14.4.7
Note:
14.4.8
Note:
Device address register (DADDR)
Bit 7 = Reserved. Forced by hardware to 0.
Bits 6:0 = ADD[6:0] Device address, 7 bits.
Software must write into this register the address sent by the host during enumeration.
This register is also reset when a USB reset is received from the USB bus or forced through
bit FRES in the CTLR register.
Endpoint n register A (EPnRA)
These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission.
They are also reset by the USB bus reset.
Endpoint 2 and the EP2RA register are not available on some devices (see device feature
list and register map).
Bit 7 = ST_OUT Status out.
This bit is set by software to indicate that a status out packet is expected: in this case, all
nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When
ST_OUT is reset, OUT transactions can have any number of bytes, as needed.
Bit 6 = DTOG_TX Data Toggle, for transmission transfers.
It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles
only when the transmitter has received the ACK signal from the USB host. DTOG_TX and
also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant
PID. They can be also written by software.
Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers.
These bits contain the information about the endpoint status, which are listed below:
DADDR
EPnRA
OUT
R/W
R/W
ST_
7
0
7
DTOG
ADD6
R/W
R/W
_TX
6
6
ADD5
STAT
_TX1
R/W
R/W
5
5
ADD4
STAT
_TX0
R/W
R/W
4
4
ADD3
TBC3
R/W
R/W
3
3
ADD2
TBC2
R/W
R/W
2
2
Reset value:
Reset value:
USB interface (USB)
ADD1
TBC1
R/W
R/W
1
1
0000 0000 (00h)
0000 xxxx (0xh)
ADD0
TBC0
R/W
R/W
0
0
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