ST7260E1 STMicroelectronics, ST7260E1 Datasheet - Page 61

• Manufacturer Part Number: ST7260E1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)
• Manufacturer: STMicroelectronics

Specifications of ST7260E1

• 4 Or 8 Kbytes Program Memory: high density Flash (HDFlash), or FastROM with readout and write protection

ST7260xx
Note:
1
2
3
4
5
Figure 37. Pulse width modulation cycle
If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Where:
t
f
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see
If the timer clock is an external clock the formula is:
Where:
t
f
The Output Compare 2 event causes the counter to be initialized to FFFCh (see
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
CPU
EXT
= Signal or pulse period (in seconds)
= CPU clock frequnency (in hertz)
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
OCiR = t
OCiR value =
= OC1R
counter
= OC2R
counter
When
When
*
f
EXT
- 5
t
PRESC
*
f
OCMP1 = OLVL1
OCMP1 = OLVL2
CPU
counter is reset
ICF1 bit is set
to FFFCh
- 5
Watchdog timer (WDG)
Table
Figure
32)
61/139
36).