ST7260 STMICROELECTRONICS [STMicroelectronics], ST7260 Datasheet
ST7260
Related parts for ST7260
ST7260 Summary of contents
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... Compares, PWM output and clock input face dows) including assembler, linker, C-compil- er, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers, HID and DFU software layers ST7260E2 8 K 384 (128) SCI 4 5.5 V SO24 ST7260 QFN40 (6x6) ST7260E1 4 K Rev. 2.0 1/117 1 ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8- bit data management, the ST7260 MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices in- clude an ST7 Core 8Kbytes of program ...
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... USBDM 4 USBV DDA OSCOUT 8 OSCIN 9 VSS 10 11 Note: NC=Do not connect PA3/EXTCLK 30 29 PA4/ICAP1/IT1 28 PA5/ICAP2/IT2 27 PA6/OCMP1/IT3 26 PA7/OCMP2/IT4 25 PB0 (10mA) 24 PB1 (10mA) 23 PB2 (10mA) 22 PB3 (10mA) 21 PB4 /IT5 (10mA ST7260 5/117 ...
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... ST7260 Figure 3. 24-Pin SO Package Pinout IT7/PB6 USBOE/PB1 6/117 USBVcc USBDM OSCOUT 23 2 USBDP OSCIN PA0/MCO 20 TDO/PC1 5 PA1 RDI/PC0 19 6 PA2 RESET (10mA) PA3/EXTCLK /TEST 9 16 PA4/ICAP1/IT1 PP PB3 (10mA PA5/ICAP2/IT2 PB2 (10mA PA7/OCMP2/IT4 ...
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... Port B1. Note 4: The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24 devices it is not available. Table 2, Table 3: / 0.7 V with input trigger will significantly improve product electro and be connected to DDA DD and . V SS ST7260 V DD 7/117 ...
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... ST7260 Table 2. Device Pin Description (QFN40) Pin n° Pin Name QFN40 OSCOUT 9 OSCIN PC2/USBOE 12 PC1/TDO 13 PC0/RDI 14 RESET PB7/IT8 18 PB6/IT7 19 V /TEST PP 20 PB5/IT6 21 PB4/IT5 22 PB3 23 PB2 24 PB1 25 PB0 26 PA7/OCMP2/IT4 27 PA6/OCMP1/IT3 28 PA5/ICAP2/IT2 29 PA4/ICAP1/IT1 30 PA3/EXTCLK 31 PA2/ICCCLK 32 NC ...
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... Reset X Port B6 Programming supply X Port B3 X Port B2 X Port B1 USB Output Enable X Port B0 X Port A7 Timer Output Compare 2 X Port A5 Timer Input Capture 2 X Port A4 Timer Input Capture 1 X Port A3 Timer External Clock Port A2 ICC Clock Port A1 ICC Data ST7260 9/117 ...
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... ST7260 Pin n° Pin Name SO24 20 PA0/MCO 21 V SSA 22 USBDP 23 USBDM 24 USBVCC 10/117 Level Port / Control Input Output I I/O I/O O Main Function Alternate Function (after reset) X Port A0 Main Clock Output Analog ground USB bidirectional data (data +) USB bidirectional data (data -) USB power supply ...
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... RAM (192 bytes) 00FFh 0100h Stack (128 Bytes) 017Fh 0180h 16-bit Addressing RAM 01BFh 8 KBytes 4 KBytes Remarks Exit from Halt Mode Internal Interrupt No Internal Interrupt No No Internal Interrupt Yes External Interrupt Yes External Interrupts Yes Internal Interrupt No CPU Interrupt Yes ST7260 11/117 ...
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... ST7260 Table 5. Hardware Register Memory Map Address Block Register Label 0000h PADR Port A 0001h PADDR 0002h PBDR Port B 0003h PBDDR 0004h PCDR Port C 0005h PCDDR 0006h to 0007h 0008h ITC ITIFRE 0009h MISC MISCR 000Ah to 000Bh 000Ch WDG WDGCR 000Dh to 0010h 0011h ...
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... USB Control Register USB Device Address Register USB Endpoint 0 Register A USB Endpoint 0 Register B USB Endpoint 1 Register A USB Endpoint 1 Register B USB Endpoint 2 Register A USB Endpoint 2 Register B Reserved (5 Bytes) Flash Control /Status Register Reserved (8 bytes) ST7260 Reset Status Remarks x0h Read only xxh R/W x0h R/W 00h R/W ...
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... ST7260 4 FLASH PROGRAM MEMORY 4.1 INTRODUCTION The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis using an external V supply. PP The HDFlash devices can be programmed and ...
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... ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case. : programming voltage PP : application board power supply (see DD 6, Note 3) APPLICATION BOARD ICC CONNECTOR HE10 CONNECTOR TYPE APPLICATION RESET SOURCE See Note 2 See Note 1 APPLICATION I/O ST7260 Fig- 15/117 ...
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... ST7260 FLASH PROGRAM MEMORY (Cont’d) 4.5 ICP (IN-CIRCUIT PROGRAMMING) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading) ...
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... Figure 7 are not (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 0 ACCUMULATOR 0 X INDEX REGISTER 0 Y INDEX REGISTER PCL 0 PROGRAM COUNTER CONDITION CODE REGISTER X 0 STACK POINTER ST7260 X = Undefined Value 17/117 ...
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... ST7260 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions ...
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... A subroutine call occupies two locations and an in- terrupt five locations in the stack area. PUSH PCH PCL PCH PCL Figure 8. POP Y IRET PCH SP PCL PCH PCH SP PCL PCL ST7260 RET or RSP 19/117 ...
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... ST7260 6 RESET AND CLOCK MANAGEMENT 6.1 RESET The Reset procedure is used to provide an orderly software start- exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external re- set at the RESET pin. A reset causes the reset vector to be fetched from ...
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... RESET (Cont’d) Figure 12. Reset Timing Diagram t DDR V DD OSCIN t OXOV f CPU PC RESET WATCHDOG RESET Note: Refer to Electrical Characteristics for values of t FFFF FFFE 4096 CPU CLOCK CYCLES DELAY , and V DDR IT+ IT- hys OXOV ST7260 21/117 ...
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... ST7260 6.2 CLOCK SYSTEM 6.2.1 General Description The MCU accepts either a Crystal or Ceramic res- onator external clock signal to drive the in- ternal oscillator. The internal clock (f rived from the external oscillator frequency (f which is divided by 3 (and for USB, de- pending on the external clock used). The internal clock is further divided setting the SMS bit in the Miscellaneous Register ...
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... All interrupts allow the processor to leave the Wait low power mode. 3. Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports (PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral reset. Table 8, "Interrupt Mapping"). ST7260 23/117 ...
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... ST7260 INTERRUPTS (Cont’d) Figure 16. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 8. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt FLASH Flash Start Programming Interrupt USB End Suspend Mode 1 ITi External Interrupts 2 TIMER Timer Peripheral Interrupts 3 4 SCI ...
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... Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control Bits ITiE bit is set, the corresponding interrupt is generated when – a rising edge occurs on the pin PA4/IT1 or PA5/ 0 IT2 or PB4/IT5 or PB5/IT6 or IT3E IT2E IT1E – a falling edge occurs on the pin PA6/IT3 or PA7/ IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere. ST7260 25/117 ...
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... ST7260 8 POWER SAVING MODES 8.1 Introduction To give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the ST7. After a RESET, the normal operating mode is se- lected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by ...
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... IF RESET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the inter- rupt routine and cleared when the CC register is popped. ST7260 ON ON OFF CLEARED RESET ...
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... ST7260 9 I/O PORTS 9.1 Introduction The I/O ports offer different functional modes: – Transfer of data through digital inputs and out- puts and for specific pins – Alternate signal input/output for the on-chip pe- ripherals – External interrupt generation An I/O port consists pins. Each pin can ...
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... IT3 Schmitt triggered input Timer OCMP2 push-pull IT4 Schmitt triggered input ALTERNATE ENABLE 1 0 ALTERNATE ENABLE 1 ALTERNATE ENABLE 0 CMOS SCHMITT TRIGGER ST7260 Alternate Function Condition MCO = 1 (MISCR) CC1 =1 CC0 = 1 (Timer CR2) IT1E = 1 (ITIFRE) IT2E = 1 (ITIFRE) OC1E = 1 IT3E = 1 (ITIFRE) OC2E = 1 IT4E = 1 (ITIFRE) ...
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... ST7260 I/O PORTS (Cont’d) Table 11. PA1, PA2 Description PORT A 1 Input PA1 without pull-up PA2 without pull-up 1 Reset State Figure 20. PA1, PA2 Configuration ALTERNATE OUTPUT DR LATCH DDR LATCH DDR SEL DR SEL 30/117 Output Very High Current open drain Very High Current open drain ...
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... USBOE (USB output ena- 2 ble) push-pull push-pull push-pull IT5 Schmitt triggered input IT4E = 1 (ITIFRE) push-pull IT6 Schmitt triggered input IT5E = 1 (ITIFRE) push-pull IT7 Schmitt triggered input IT6E = 1 (ITIFRE) push-pull IT8 Schmitt triggered input IT7E = 1 (ITIFRE) ST7260 Alternate Function Condition USBOE =1 (MISCR) 31/117 ...
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... ST7260 Figure 21. Port B Configuration ALTERNATE OUTPUT DR LATCH DDR LATCH DDR SEL DR SEL ALTERNATE INPUT 32/117 ALTERNATE ENABLE 1 0 ALTERNATE ENABLE 1 ALTERNATE ENABLE DIGITAL ENABLE P-BUFFER PAD DIODES N-BUFFER V SS ...
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... RDI (SCI input) push-pull TDO (SCI output) USBOE (USB output ena- push-pull ble) ALTERNATE ENABLE 1 0 ALTERNATE ENABLE 1 ALTERNATE ENABLE 0 CMOS SCHMITT TRIGGER Alternate Function Signal Condition SCI enable USBOE =1 (MISCR P-BUFFER V DD PULL-UP N-BUFFER DIODES V SS ST7260 PAD 33/117 ...
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... ST7260 I/O PORTS (Cont’d) 9.2.4 Register Description DATA REGISTERS (PxDR) Port A Data Register (PADR): 0000h Port B Data Register (PBDR): 0002h Port C Data Register (PCDR): 0004h Read/Write Reset Value Port A: 0000 0000 (00h) Reset Value Port B: 0000 0000 (00h) Reset Value Port C: 1111 x000 (FXh) Note: For Port C, unused bits (7-3) are not acces- sible ...
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... Unused bits 7-4 are set. Bit 0 = MCO Main Clock Out selection This bit enables the MCO alternate function on the PA0 I/O port set and cleared by software. 0: MCO alternate function disabled (I/O pin free for Fig- general-purpose I/O) 1: MCO alternate function enabled (f port) ST7260 on I/O CPU 35/117 ...
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... ST7260 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the counter’ ...
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... HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 11.1.7 Interrupts None. ST7260 37/117 ...
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... ST7260 WATCHDOG TIMER (Cont’d) 11.1.8 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by Table 16. Watchdog Timer Register Map and Reset Values Address Register 7 Label (Hex.) ...
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... CR2 register, as illustrated in "Clock Control ister repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can external frequency. Figure 24. ST7260 Table 17, Bits". The value in the counter reg- /2, f /4, f CPU CPU CPU 39/117 ...
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... ST7260 16-BIT TIMER (Cont’d) Figure 24. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See note) TIMER INTERRUPT 40/117 ST7 INTERNAL BUS MCU-PERIPHERAL INTERFACE ...
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... The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. ST7260 41/117 ...
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... ST7260 16-BIT TIMER (Cont’d) Figure 25. Counter Timing Diagram, Internal Clock Divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 26. Counter Timing Diagram, Internal Clock Divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 27 ...
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... ICIE bit is set. This can be avoided if the input capture func- tion i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt genera- tion in order to measure events that go beyond the timer range (FFFFh). ST7260 Figure 29). 43/117 ...
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... ST7260 16-BIT TIMER (Cont’d) Figure 28. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 29. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The rising edge is the active edge. ...
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... Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFi bit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFi bit). ST7260 ∆t f ∆ * CPU ...
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... ST7260 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set ...
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... COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = TIMER CPU TIMER CLOCK 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 = f /4 TIMER CPU TIMER CLOCK 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 ST7260 2ED3 2ED3 47/117 ...
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... ST7260 16-BIT TIMER (Cont’d) 11.2.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. ...
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... FFFC FFFD FFFE OLVL2 FFFC FFFD FFFE OLVL2 2ED3 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 OLVL1 OLVL2 compare1 2ED0 2ED1 2ED2 34E2 OLVL1 OLVL2 compare1 compare2 ST7260 FFFC 49/117 ...
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... ST7260 16-BIT TIMER (Cont’d) 11.2.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R regis- ter, and so this functionality can not be used when PWM mode is activated ...
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... Input Capture 1 Input Capture 2 Yes Yes Not Recommended No Not Recommended Enable Exit Event Control from Flag Bit Wait ICF1 ICIE ICF2 OCF1 Yes OCIE OCF2 TOF TOIE Output Compare 1 Output Compare 2 Yes Yes 1) Partially ST7260 Exit from Halt No 2) 51/117 ...
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... ST7260 16-BIT TIMER (Cont’d) 11.2.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) ...
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... A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register falling edge triggers the counter register rising edge triggers the counter register. ST7260 CC1 CC0 ...
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... ST7260 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode ...
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... CHR register LSB MSB OUTPUT COMPARE (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register LSB MSB ST7260 1 HIGH REGISTER 0 LSB 1 LOW REGISTER 0 LSB 55/117 ...
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... ST7260 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register ...
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... ST7260 1 0 EXEDG 0 0 OLVL1 LSB LSB - LSB LSB LSB LSB LSB LSB 0 0 LSB LSB - LSB LSB 0 0 57/117 ...
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... ST7260 11.3 SERIAL COMMUNICATIONS INTERFACE (SCI) 11.3.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range of baud rates using two baud rate generator systems. ...
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... TE RE RWU SBK /PR /16 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 BAUD RATE GENERATOR (DATA REGISTER) DR Received Shift Register CR1 M PCE PS PIE WAKE RECEIVER RECEIVER CONTROL TDRE TC RDRF IDLE TRANSMITTER RATE CONTROL BRR RECEIVER RATE CONTROL ST7260 CLOCK SR PE 59/117 ...
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... ST7260 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 35 It contains 6 dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR) Refer to the register descriptions in for the definitions of each bit ...
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... Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR. ST7260 61/117 ...
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... ST7260 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin ...
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... SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode. ST7260 63/117 ...
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... ST7260 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.4.6 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 19 ...
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... The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set. sampled values 7/16 One bit time 6/16 7/16 ST7260 Section 16 65/117 ...
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... ST7260 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.3.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmit- HALT ting/receiving until Halt mode is exit- ed. 11.3.6 Interrupts The SCI interrupt events are connected to the same interrupt vector ...
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... Bit Parity error. This bit is set by hardware when a parity error oc- curs in receiver mode cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An inter- rupt is generated if PIE=1 in the SCICR1 register parity error 1: Parity error ST7260 67/117 ...
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... ST7260 SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit Transmit data bit 8. This bit is used to store the 9th bit of the transmit- ted word when M=1 ...
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... This bit set is used to send break characters set and cleared by software break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word. ST7260 69/117 ...
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... ST7260 SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR) ...
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... R8 T8 SCID TIE TCIE RIE DR3 DR2 DR1 SCT0 SCR2 SCR1 WAKE PCE ILIE TE RE RWU ST7260 DR0 x x SCR0 PIE 0 0 SBK 0 0 71/117 ...
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... ST7260 11.4 USB INTERFACE (USB) 11.4.1 Introduction The USB Interface implements a low-speed func- tion interface between the USB and the ST7 mi- crocontroller highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components are needed apart from the external pull-up on USBDM for low speed recognition by the USB host ...
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... Note: Not valid for data transmission. 101111 101000 100111 100000 011111 011000 010111 010000 001111 001000 000111 000000 DA6 EP1 EP0 CNT3 CNT2 Figure Endpoint 2 TX Endpoint 2 RX Endpoint 1 TX Endpoint 1 RX Endpoint 0 TX Endpoint 0 RX ST7260 0 CNT1 CNT0 39. 73/117 ...
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... ST7260 USB INTERFACE (Cont’d) PID REGISTER (PIDR) Read only Reset Value: xx00 0000 (x0h) 7 TP3 TP2 Bits 7:6 = TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2. Note: PID bits 1 & 0 have a fixed value of 01. ...
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... USB interface, just RESET sequence came SPM ETM M from the USB. 0: Reset not forced 1: USB interface reset forced. The USB is held in RESET state until software clears this bit, at which point a “USB-RESET” in- terrupt will be generated if enabled RESUME PDWN FSUSP ST7260 0 FRES 75/117 ...
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... ST7260 USB INTERFACE (Cont’d) DEVICE ADDRESS REGISTER (DADDR) Read / Write Reset Value: 0000 0000 (00h ADD6 ADD5 ADD4 ADD3 Bit 7 = Reserved. Forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration. ...
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... Bits 3:0 = Forced by hardware to 0. result in a STAT_RX0 Meaning NAK: the endpoint is na- ked and all reception re- 0 quests result in a NAK handshake. VALID: this endpoint is 1 enabled for reception. DTOG STAT STAT RX1 RX0 ST7260 77/117 ...
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... ST7260 USB INTERFACE (Cont’d) 11.4.5 Programming Considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with the Interrupt Status Register (IS- TR) bits ...
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... DTOG_RX STAT_RX1 STAT_RX0 DTOG_TX STAT_TX1 STAT_TX0 DTOG_RX STAT_RX1 STAT_RX0 DTOG_TX STAT_TX1 STAT_TX0 DTOG_RX STAT_RX1 STAT_RX0 ST7260 RX_SEZ RXD DA11 DA10 DA9 CNT3 CNT2 CNT1 IOVR ESUSP RESET IOVRM ESUSPM RESETM ...
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... ST7260 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset The ST7 Instruction set is designed to minimize the number of bytes required per instruction Table 22 ...
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... The pointer address is a byte, the pointer size is a byte, thus allowing addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. ST7260 81/117 ...
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... ST7260 ST7 ADDRESSING MODES (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register value ( with a pointer value located in memory. The point- er address follows the opcode ...
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... It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode one. ST7260 NEG MUL RRC SWAP SLA CALL CALLR ...
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... ST7260 INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL Call subroutine CALLR Call subroutine relative ...
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... S/W interrupt XOR M A Src reg reg ST7260 85/117 ...
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... ST7260 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the ...
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... V according to their reset configuration maximum cannot be IN value. A positive injection is induced the absolute sum of the positive INJ(PIN) Value -65 to +150 for T Jmax ST7260 Unit V Unit mA µA > maxi- INJ(PIN) Unit °C 87/117 ...
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... ST7260 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions Symbol Parameter V Operating Supply Voltage DD V Analog supply voltage DDA V Analog supply voltage SSA Operating frequency f CPU Ambient temperature range T A Figure 42. f Maximum Operating Frequency Versus V CPU f [MHz] CPU 8 4 FUNCTIONALITY 2 NOT GUARANTEED IN THIS AREA 0 2 ...
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... CPU 1) MHz 7.5 9 CPU MHz 10.5 13 CPU MHz 6 8 CPU MHz 8.5 11 CPU 25 40 100 120 230 in WAIT at 4 and 8 MHz f DD Idd WFI (mA) at fcpu=4 and 8MHz 4.2 4.4 4.6 4.8 5 5.2 Vdd (V) ST7260 Unit µA µA CPU 8MHz 4MHz 5.4 89/117 ...
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... ST7260 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆t the current instruction execution. ...
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... C L2 Conditions 1) see Figure 45 1) ≤V ≤ 90% 10 f(OSCIN) w(OSCINH) OSCOUT Not connected internally OSCIN OSCIN RESONATOR R F OSCOUT ST7260 Min Typ Max 0.7xV 0.3xV ±1 t w(OSCINL) f OSC I L ST72XXX OSC ST72XXX Unit ...
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... ST7260 13.6 MEMORY CHARACTERISTICS Subject to general operating conditions for f 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM Note: 1. Guaranteed by design. Not tested in production. 13.6.2 Flash Memory Operating Conditions MHz. CPU DUAL VOLTAGE FLASH MEMORY Symbol Parameter f Operating Frequency CPU V Programming Voltage ...
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... T =+25° Conditions = =+25 ° MHz, A OSC = =+25 ° MHz, A OSC Max vs. [f Monitored OSC f Frequency Band CPU 16/8 MHz 0.1MHz to 30MHz 36 30MHz to 130MHz 39 130MHz to 1GHz 26 SAE EMI Level 3.5 ST7260 Level/ Class Unit ] dBµV - 93/117 ...
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... ST7260 EMC CHARACTERISTICS (Cont’d) 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to the application note AN1181. Absolute Maximum Ratings ...
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... Static peak current value taken at a fixed V ST72XXX UNUSED I/O PORT 5 5.2 5.4 unless otherwise specified. A Min Typ Max 0.3xV 0.7xV 400 400 50 90 120 current characteristics de- PU UNUSED I/O PORT 10kΩ ST72XXX ST7260 Unit ±1 µA kΩ CPU value, IN and tem- DD 95/117 ...
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... ST7260 Figure 50. Typ Rpu (KOhm) 140 120 100 4.2 4.4 4.6 4.8 Vdd (V) 13.8.2 Output Driving Current Subject to general operating condition for V Symbol Parameter Output low level voltage for a standard I/O pin when pins are sunk at the same time, Port A0, Port A(3:7), Port C(0:2) ...
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... Figure 55 0.6 0.59 0.58 0.57 0.56 0.55 0.54 0.53 0.52 0.51 0 Figure 56 0.8 0.75 0.7 0.65 0 5.2 5.4 Figure 58 1.8 1.6 1.4 1.2 1 0.8 0.6 0 high sink vs Vol_10mA (V) at Iio=10mA 4.2 4.4 4.6 4.8 5 5.2 Vdd (V) very high sink vs Vol_25mA (V) at Iio=25mA 4.2 4.4 4.6 4.8 5 5.2 Vdd ( (high current |Vdd - Voh| (V) at Vdd= -Iio (mA) ST7260 5.4 5.4 97/117 ...
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... ST7260 Figure 59 (low current |Vdd - Voh| (V) at Iio=-2mA 0.165 0.16 0.155 0.15 0.145 0.14 0.135 0.13 0.125 0.12 4 4.2 4.4 4.6 4.8 Vdd (V) 98/117 Figure 60. |V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 5.2 5 =10mA (high current |Vdd - Voh| (V) at Iio=-10mA 4.2 4.4 4.6 4.8 5 5.2 Vdd (V) 5.4 ...
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... External pin or internal reset sources 4) . VSS can be ignored. h(RSTL)in unless otherwise specified. A Min Typ Max 0.7xV 0.3xV SS 400 = 100 Section 13.2 and the sum of I ST7260 Unit 0.8 V 1.3 kΩ 1/f SFOSC µs µs (I/ IO 99/117 ...
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... ST7260 CONTROL PIN CHARACTERISTICS (Cont’d) Figure 61. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01 µF Figure 62. RESET pin protection when LVD is disabled. Recommended for EMC V DD 0.0 1µF USER EXTERNAL RESET CIRCUIT 0.01 µF Required Note 1: – The reset network protects the device against parasitic resets. ...
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... For more detailed information, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1). = 4.0 to 5.25V unless otherwise specified) DD Conditions I(D+, D-) Includes VDI range 1.5 Kohms to 3. Kohms Crossover points tr Conditions 1) CL= CL=600 pF 1) CL= CL=600 pF tr/tf ST7260 Min. Max. Unit 0.2 0.8 2.5 0.8 2 0.3 2.8 3.6 3.00 3.60 Min Max Unit 75 ns 300 300 ns 80 120 % 1.3 2.0 ...
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... ST7260 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 13.10.2 SCI - Serial Communications Interface Subject to general operating condition for V Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO). Symbol Parameter f Tx Communication frequency 8 MHz ~0.16 102/117 , f , and T unless otherwise specified. ...
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... inches Dim. Min Typ Max Min A 2.35 2.65 0.093 A1 0.10 0.30 0.004 C B 0.33 0.51 0.013 C 0.23 0.32 0.009 D 15.20 15.60 0.599 E 7.40 7.60 0.291 e 1.27 H 10.00 10.65 0.394 h 0.25 0.75 0.010 α 0° 8° 0° L 0.40 1.27 0.016 Number of Pins N 24 ST7260 Typ Max 0.104 0.012 0.020 0.013 0.614 0.299 0.050 0.419 0.030 8° 0.050 103/117 ...
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... ST7260 Figure 65. 40-Lead Very thin Fine pitch Quad Flat No-Lead Package A SEATING PLANE A1 PIN #1 ID TYPE C RADIUS 104/117 inches Dim. Min Typ Max Min Typ A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0.02 0.05 0.001 0.002 A2 0.65 1.00 0.026 0.039 A3 0.20 0.008 b 0.18 0.25 0.30 0.007 0.010 0.012 D 5 ...
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... PORT 2. The average chip-junction temperature can be obtained from the formula T Ratings SO24 QFN40 where P D INT PORT J ST7260 Value Unit 70 °C/W 34 500 mW 150 °C is the chip internal power (I INT RthJA. ...
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... ST7260 14.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 66 Figure 66. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 Temp. [°C] 100 PREHEATING PHASE Figure 67. Recommended Reflow Soldering Oven Profile (MID JEDEC) 250 200 150 Temp. [° ...
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... FMP_R option is selected, causes the OSC FMP_ -- whole user memory to be erased first and the de- 24/12 R vice can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and on page 14 0: Read-out protection enabled 1: Read-out protection disabled ST7260 section 4.3.1 for more details. 107/117 ...
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... Table 25. Supported Part Numbers 1) Sales Type ST72F60K2U1 ST72F60E2M1 ST72F60K1U1 ST72F60E1M1 ST7260K2U1/xxx ST7260E2M1/xxx ST7260K1U1/xxx ST7260E1M1/xxx ST72P60K2U1 ST72P60E2M1 ST72P60K1U1 ST72P60E1M1 Note: Contact ST sales office for product availability 1. /xxx stands for the ROM code name assigned by STMicroelectronics 108/117 Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred ...
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... Three types of development tool are offered by ST see Table 26 Programming Capability No Yes (All packages) Evaluation Board ST7 Emulator ST7MDTULS-EVAL ST7MDTU3-EMU3 ST7260 and Table 27 for more details. 1) Software Included ST7 CD ROM with: – ST7 Assembly toolchain – STVD7 powerful Source Level Debugger for Win 3.1, Win 9x and NT – ...
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... Please download the latest version of this option list from: http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list 110/117 ST7260 MICROCONTROLLER OPTION LIST (Last update: Oct 2006 ST7260E2M1 | | [ ] ST7260K2U1 | | ST72P60E2M1 | | [ ] ST72P60K2U1 ...
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... TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS AN1753 SOFTWARE UART USING 12-BIT ART ST7260 111/117 ...
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... ST7260 Table 28. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK REFERENCE NOTE ...
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... ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY SYSTEM OPTIMIZATION AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09 AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC ST7260 113/117 ...
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... Reset and Set TE (IDLE request) - Set and Reset SBK (Break Request) - Re-enable interrupts 16.4 USB Behavior with LVD Disabled On ROM devices, if the LVD is disabled, the USB is disabled by hardware. So, the LVD is forced (LVD enabled). Refer to the ST7260 option list for details. ...
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... Device package example Silicon Rev Trace code xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ST7xxxxxxxxx TYPE xxxxxxxxxxx$x7 XX Total Qty XXXXXXXXX XX XX Trace code Silicon Rev Marking B XXXXXXXXXX Bulk ID XXXXXXXXXXXX Example box label ST7260 115/117 ...
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... ST7260 17 REVISION HISTORY Date Revision 13-Feb-2006 1 Initial release 02-Nov-2006 2 Added Known Limitations section (with new PA2 limitation) 116/117 Main Changes ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST7260 117/117 ...