AD5361 Analog Devices, AD5361 Datasheet - Page 5

• Manufacturer Part Number: AD5361
• Description: 16-Channel, 14-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5361

• Resolution (bits): 14bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Parameter
DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC)
TEMPERATURE SENSOR (TEMP_OUT)
POWER REQUIREMENTS
1
2
3
4
AC CHARACTERISTICS
DV
DAC offset registers at default value; all specifications T
Table 2.
Parameter
DYNAMIC PERFORMANCE
1
Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
Specifications are guaranteed for a 5 V reference only.
VOUTx refers to any of VOUT0 to VOUT15.
Guaranteed by design and characterization, not production tested.
Guaranteed by design and characterization, not production tested.
Output Low Voltage
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance
Accuracy
Output Voltage at 25°C
Output Voltage Scale Factor
Output Load Current
Power-On Time
DV
V
V
Power Supply Sensitivity
DI
I
I
Power-Down Mode
Power Dissipation
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 10 kHz
DD
SS
DD
SS
CC
CC
∆ Full Scale/∆ V
∆ Full Scale/∆ V
∆ Full Scale/∆ DV
DI
I
I
Power Dissipation Unloaded (P)
Junction Temperature
CC
DD
SS
= 2.5 V; V
CC
DD
= 15 V; V
DD
SS
CC
4
1
SS
= −15 V; V
4
4
REF
= 5 V; AGND = DGND = SIGGND = 0 V; C
B Version
0.5
DV
±5
10
±1
±5
1.46
4.4
200
10
2.5/5.5
8/16.5
−4.5/−16.5
−75
−75
−90
2
10
10
5
35
−35
245
130
20
B Version
30
1
5
10
100
10
0.2
0.02
250
CC
− 0.5
1
1
MIN
Unit
V max
V min
μA max
pF typ
°C typ
°C typ
V typ
mV/°C typ
μA max
ms typ
V min/max
V min/max
V min/max
dB typ
dB typ
dB typ
mA max
mA max
mA max
μA typ
μA typ
μA typ
mW max
°C max
to T
Unit
μs typ
μs max
V/μs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
Rev. A | Page 5 of 28
MAX
, unless otherwise noted.
Test Conditions/Comments
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s
VREF0, VREF1 = 2 V p-p, 1 kHz
Effect of input bus activity on DAC output under test
VREF0 = VREF1 = 0 V
Test Conditions/Comments
SDO only
Bit 0 in the Control Register is 1
T
Sinking 200 μA
Sourcing 200 μA
@ 25°C
−40°C < T < +85°C
Current source only
To within ±5°C
V
Outputs unloaded
Outputs unloaded
V
CC
SS
J
= T
= −12 V, V
= 5.5 V, V
A
+ P
TOTAL
L
= 200 pF; R
IH
DD
= DV
× θ
= +12 V, DV
JA
CC
, V
IL
L
= GND
= 10 kΩ; gain (M), offset (C), and
CC
= 2.5 V
AD5360/AD5361