AD5361 Analog Devices, AD5361 Datasheet - Page 15

• Manufacturer Part Number: AD5361
• Description: 16-Channel, 14-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5361

• Resolution (bits): 14bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE
The AD5360/AD5361 contain 16 DAC channels and 16 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit resistor-string DAC in the case of
the AD5360 and a 14-bit DAC in the case of the AD5361,
followed by an output buffer amplifier. The resistor-string
section is simply a string of resistors, of equal value, from
VREF0 or VREF1 to AGND. This type of architecture
guarantees DAC monotonicity. The 16-/14-bit binary digital
code loaded to the DAC register determines at which node
on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the
DAC output voltage by 4. The nominal output span is 12 V
with a 3 V reference and 20 V with a 5 V reference.
Table 6. AD5360/AD5361 Registers
Register Name
X1A (group) (channel)
X1B (group) (channel)
M (group) (channel)
C (group) (channel)
X2A (group) (channel)
X2B (group) (channel)
DAC (group) (channel)
OFS0
OFS1
Control
Monitor
GPIO
Table 7. AD5360/AD5361 Input Register Default Values
Register Name
X1A, X1B
M
C
OFS0, OFS1
Control
A/B Select 0 and A/B Select 1
Word Length in Bits
16 (14)
16 (14)
16 (14)
16 (14)
16 (14)
16 (14)
14
14
5
6
2
AD5360 Default Value
0x8000
0xFFFF
0x8000
0x2000
0x00
0x00
Description
Input Data Register A, one for each DAC channel.
Input Data Register B, one for each DAC channel.
Gain trim register, one for each DAC channel.
Offset trim register, one for each DAC channel.
Output Data Register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
Output Data Register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable or directly writable.
Offset DAC 0 data register, sets offset for Group 0.
Offset DAC 1 data register, sets offset for Group 1.
Control register.
Monitor enable and configuration register.
GPIO configuration register.
Rev. A | Page 15 of 28
CHANNEL GROUPS
The 16 DAC channels of the AD5360/AD5361 are arranged into
two groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 derives its refer-
ence voltage from VREF1. Each group has its own signal
ground pin.
AD5361 Default Value
0x2000
0x3FFF
0x2000
0x2000
0x00
0x00
AD5360/AD5361