AD5025 Analog Devices, AD5025 Datasheet - Page 23

• Manufacturer Part Number: AD5025
• Description: Fully Accurate 12-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
• Manufacturer: Analog Devices

Specifications of AD5025

• Resolution (bits): 12bit
• Dac Update Rate: 1.5MSPS
• Dac Settling Time: 10.7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

MICROPROCESSOR INTERFACING
AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x
Interface
Figure 46 shows a serial interface between the AD5025/AD5045/
AD5065 and the Blackfin® ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5025/AD5045/AD5065, the setup for the interface is
as follows: DT0PRI drives the DIN pin of the AD5025/AD5045/
AD5065, and TSCLK0 drives the SCLK of the parts. The SYNC is
driven from TFS0.
AD5025/AD5045/AD5065 to 68HC11/68L11 Interface
Figure 47 shows a serial interface between the AD5025/AD5045/
AD5065 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5025/AD5045/AD5065,
and the MOSI output drives the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5025/AD5045/
AD5065, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
Figure 46. AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Interface
Figure 47. AD5025/AD5045/AD5065 to 68HC11/68L11 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11/68L11*
ADSP-BF53x*
TSCLK0
DT0PRI
MOSI
TFS0
SCK
PC7
SYNC
DIN
SCLK
SYNC
SCLK
DIN
AD5065
AD5065
AD5025/
AD5045/
AD5025/
AD5045/
*
*
Rev. 0 | Page 23 of 28
AD5025/AD5045/AD5065 to 80C51/80L51 Interface
Figure 48 shows a serial interface between the AD5025/AD5045/
AD5065 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5025/AD5045/AD5065, and RxD drives the serial
data line of the part. The SYNC signal is again derived from a
bit-programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5025/AD5045/
AD5065, P3.3 is taken low. The 80C51/80L51 transmits data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is lept low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in LSB-first format. The AD5025/AD5045/AD5065
must receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
AD5025/AD5045/AD5065 to MICROWIRE Interface
Figure 49 shows an interface between the AD5025/AD5045/
AD5065 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5025/AD5045/AD5065 on the rising edge of SCLK.
Figure 48. AD5025/AD5045/AD5065 to 80C51/80L51 Interface
Figure 49. AD5025/AD5045/AD5065 to MICROWIRE Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51*
MICROWIRE*
P3.3
RxD
TxD
SO
CS
SK
AD5025/AD5045/AD5065
SYNC
SCLK
DIN
SYNC
DIN
SCLK
AD5065
AD5065
AD5025/
AD5045/
AD5025/
AD5045/
*
*