AD5025 Analog Devices, AD5025 Datasheet - Page 19

• Manufacturer Part Number: AD5025
• Description: Fully Accurate 12-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
• Manufacturer: Analog Devices

Specifications of AD5025

• Resolution (bits): 12bit
• Dac Update Rate: 1.5MSPS
• Dac Settling Time: 10.7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

STANDALONE MODE
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5025/AD5045/AD5065 compatible
with high speed DSPs. On the 32
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
the mode of operation. The SYNC line must be brought high
within 30 ns of the 32
must be brought high for a minimum of 1.9 μs before the next
write sequence so that a falling edge of SYNC can initiate the next
write sequence. Because the SYNC buffer draws more current
when V
idled low between write sequences for even lower power
operation of the part. As mentioned previously, however, SYNC
must be brought high again just before the next write sequence.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32
32
The input register is reset, and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operating mode occurs (see Figure 44).
DAISY-CHAINING
For systems that contain several DACs, or where the user wishes to
read back the DAC contents for diagnostic purposes, the SDO
pin can be used to daisy-chain several devices together and
provide serial readback.
The daisy-chain mode is enabled through a software executable
daisy-chain enable (DCEN) command. Command 1000 is
reserved for this DCEN function (see Table 8). The daisy-chain
mode is enabled by setting a bit (DB1) in the DCEN register.
The default setting is standalone mode, where DB1 = 0.
Table 10. 32-Bit Input Register Contents for Daisy-Chain Enable
MSB
DB31 to DB28
X
Don’t cares
nd
nd
falling edge. However, if SYNC is brought high before the
falling edge, this acts as an interrupt to the write sequence.
SYNC
SCLK
DIN
IN
= V
DD
SYNC HIGH BEFORE 32
than it does when V
DB31
INVALID WRITE SEQUENCE:
DB27
1
nd
falling edge of SCLK. In either case, it
Command bits (C3 to C0)
DB26
0
ND
nd
FALLING EDGE
falling clock edge, the last
IN
= 0 V, SYNC should be
DB0
DB25
0
DB24
0
Figure 44. SYNC Interrupt Facility
DB23
X
Rev. 0 | Page 19 of 28
Address bits (A3 to A0)
DB22
X
Table 9 shows how the state of the bit corresponds to the mode
of operation of the device.
Table 9. DCEN (Daisy-Chain Enable) Register
DB1
0
1
The SCLK is continuously applied to the input register when
SYNC is low. If more than 32 clock pulses are applied, the data
ripples out of the input shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next DAC in the chain, a multiDAC interface is
constructed. Each DAC in the system requires 32 clock pulses;
therefore, the total number of clock cycles must equal 32N,
where N is the total number of devices in the chain.
If SYNC is taken high before 32N clocks are clocked into the
part, it is considered an invalid frame and the data is discarded.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the input register.
The serial clock can be continuous or a gated clock. A continuous
SCLK source can be used only if SYNC can be held low for the
correct number of clock cycles. In gated clock mode, a burst
clock containing the exact number of clock cycles must be used,
and SYNC must be taken high after the final clock to latch the data.
In daisy-chain mode, the LDAC pin cannot be tied permanently
low. The LDAC pin must be used in asynchronous LDAC update
mode, as shown in Figure 3. The LDAC pin must be brought
high after pulsing. This allows all DAC outputs to simultaneously
update.
VALID WRITE SEQUENCE, OUTPUT UPDATES
DB21
X
DB31
ON THE 32
DB0
X
X
ND
DB20
X
FALLING EDGE
AD5025/AD5045/AD5065
Description
Standalone mode (default)
DCEN mode
DB0
DB2 to DB19
X
Don’t cares
DB1
1/0
DCEN register
DB0
X
LSB