AD5025 Analog Devices, AD5025 Datasheet - Page 21

• Manufacturer Part Number: AD5025
• Description: Fully Accurate 12-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
• Manufacturer: Analog Devices

Specifications of AD5025

• Resolution (bits): 12bit
• Dac Update Rate: 1.5MSPS
• Dac Settling Time: 10.7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

CLEAR CODE REGISTER
The AD5025/AD5045/AD5065 have a hardware CLR pin that
is an asynchronous clear input. The CLR input is falling edge sensi-
tive. Bringing the CLR line low clears the contents of the input
register and the DAC registers to the data contained in the user-
configurable CLR register, and sets the analog outputs accordingly
(see Table 13). This function can be used in system calibration
to load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the input register (see Table 13).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 8).
Table 13. Clear Code Register
DB1 (CR1)
0
0
1
1
The part exits clear code mode on the 32
next write to the part. If CLR is activated during a write sequence,
the write is aborted.
The CLR pulse activation time, the falling edge of CLR to when
the output starts to change, is typically 10.6 μs (see Figure 31).
See Table 14 for contents of the input register during the
loading clear code register operation.
Table 14. 32-Bit Input Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
Table 15. LDAC Overwrite Definitions
LDAC Bits (DB3 and DB0)
0
1
1
Table 16. 32-Bit Input Register Contents for LDAC Overwrite Function
MSB
DB31 to DB28
X
Don’t cares
X = don’t care.
Clear Code Register
Load DAC Register
DB27
0
DB27
0
DB0 (CR0)
0
1
0
1
Command bits (C3 to C0)
Command bits (C3 to C0)
DB26
1
DB26
1
LDAC Pin
1, 0
X
1
DB25
1
DB25
0
Clears to Code
0x0000
0x8000
0xFFFF
No operation
nd
DB24
0
falling edge of the
DB24
1
LDAC Operation
Determined by LDAC pin.
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
DB23
X
Address bits (A3 to A0)—don’t cares
DB23
X
DB22
X
Rev. 0 | Page 21 of 28
Address bits (A3 to A0)
DB22
X
DB21
X
LDAC FUNCTION
Hardware LDAC Pin
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin. The LDAC pin can be used in
synchronous or asynchronous mode, as shown in Figure 3.
Synchronous LDAC : LDAC is held low. After new data is read,
the DAC registers are updated on the falling edge of the 32
SCLK pulse. LDAC can be permanently low or pulsed in
standalone mode. LDAC cannot be tied permanently low in
daisy-chain mode.
Asynchronous LDAC : LDAC is held high and pulsed. The outputs
are not updated at the same time that the input registers are
written to. When LDAC goes low, the DAC registers are updated
with the contents of the input register.
Software LDAC Function
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software LDAC function by writing to Input
Register n (see Table 7) and updating all DAC registers.
Command 0010 is reserved for this software LDAC function.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 16). Setting the LDAC
bit register (DB0 to DB3) to 0 for a DAC channel means that
this channel update is controlled by the hardware LDAC pin.
If DB0 or DB3 is set to 1, this channel updates synchronously.
The part effectively sees the hardware LDAC pin as being tied
low (see Table 15 for the LDAC register mode of operation).
This flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
DB20
X
X
DB21
DB4 to DB19
X
Don’t cares
DB20
X
AD5025/AD5045/AD5065
X
DB2 to DB19
Don’t cares
DB3
DAC B
Set LDAC bits to 1 to override LDAC pin
DB2
X
1/0
DB1
Clear code register
DB1
X
(CR1 to CR0)
DB0
1/0
DB0
DAC A
nd
LSB
LSB