AD5025 Analog Devices, AD5025 Datasheet - Page 20

• Manufacturer Part Number: AD5025
• Description: Fully Accurate 12-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
• Manufacturer: Analog Devices

Specifications of AD5025

• Resolution (bits): 12bit
• Dac Update Rate: 1.5MSPS
• Dac Settling Time: 10.7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5025/AD5045/AD5065
POWER-ON RESET AND SOFTWARE RESET
The AD5025/AD5045/AD5065 contain a power-on reset (POR)
circuit that controls the output voltage during power-up. By
connecting the POR pin low, the AD5025/AD5045/AD5065
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5025/AD5045/AD5065 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code selected by the POR pin. Command 0111 is reserved
for this reset function (see Table 8).
POWER-DOWN MODES
The AD5025/AD5045/AD5065 contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the input register (see
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device.
Table 11. Modes of Operation
DB9
0
0
1
1
When both Bit DB9 and Bit DB8 in the input register are set to 0,
the part works normally with its normal power consumption of
2.2 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 μV at 5 V. Not only does the supply
Table 12. 32-Bit Input Register Contents for Power-Up/Power-Down Function
MSB
DB31
to
DB28
X
Don’t
cares
DB27
0
DB8
0
1
0
1
Command bits (C2 to C0)
DB26
1
Operating Mode
Normal operation, power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
DB25
0
DB24
0
DB23
X
Address bits (A3 to A0)—don’t
DB22
X
cares
DB21
X
Rev. 0 | Page 20 of 28
DB20
X
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different options. The output is connected internally to GND
through either a 1 kΩ or a 100 kΩ resistor, or it is left open-
circuited (three-state). The output stage is illustrated in Figure 45.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 4.5 μs for V
Either or both DACs (DAC A and DAC B) can be powered down
to the selected mode by setting the corresponding bits (DB3 and
DB0) to 1. See Table 12 for the contents of the input register
during power-down/power-up operation.
Any combination of DACs can be powered up by setting PD1 = 0
and PD0 = 0 (normal operation). The output powers up to the
value in the input register ( LDAC low) or to the value in the
DAC register before powering down ( LDAC high).
DB10
to
DB19
X
Don’t
cares
DB9
PD1
Power-down
DAC
mode
Figure 45. Output Stage During Power-Down
DB8
PD0
DD
POWER-DOWN
AMPLIFIER
CIRCUITRY
DB4
to
DB7
X
Don’t
cares
= 5 V (see Figure 24).
DB3
DAC
B
Power-down/power-up channel
selection—set bits to 1 to select
DB2
DAC
B
RESISTOR
NETWORK
DB1
DAC
A
V
OUT
DB0
DAC A
LSB