AD7799 Analog Devices, AD7799 Datasheet - Page 18

• Manufacturer Part Number: AD7799
• Description: 3-Channel, Low Noise, Low Power, 24-Bit, Sigma Delta ADC with On-Chip In-Amp
• Manufacturer: Analog Devices

Specifications of AD7799

• Resolution (bits): 24bit
• # Chan: 3
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7798/AD7799
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7798/AD7799 are low power ADCs that each incorporate
a ∑-Δ modulator, a buffer, an in-amp, and on-chip digital filtering
intended for the measurement of wide dynamic range, low
frequency signals, such as those in pressure transducers and
weigh scales.
Each part has three differential inputs that can be buffered or
unbuffered. The reference is provided by an external reference
source. Figure 11 shows the basic connections required to
operate the parts.
The output rate of the AD7798/AD7799 (f
mable. The allowable update rates, along with the corresponding
settling times, are listed in Table 14. Normal mode rejection is
the major function of the digital filter. Simultaneous 50 Hz and
60 Hz rejection is optimized when the update rate equals 16.7 Hz
or less, because notches are placed at both 50 Hz and 60 Hz with
these update rates (see Figure 13).
The AD7798/AD7799 use slightly different filter types,
depending on the output update rate, so that the rejection of
quantization noise and device noise is optimized. When the
update rate ranges from 4.17 Hz to 12.5 Hz, a sinc3 filter, along
with an averaging filter, is used. When the update rate ranges
from 16.7 Hz to 39 Hz, a modified sinc3 filter is used. This filter
gives simultaneous 50 Hz and 60 Hz rejection when the update
rate equals 16.7 Hz. A sinc4 filter is used when the update rate
ranges from 50 Hz to 242 Hz. Finally, an integrate-only filter is
used when the update rate equals 470 Hz. Figure 12 through
Figure 15 show the frequency responses of the different filter
types for a few of the update rates.
OUT–
IN+
IN–
AV
DD
OUT+
ADC
) is user-program-
REFIN(+)
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
REFIN(–)
PSW
GND
Figure 11. Basic Connection Diagram
MUX
AV
DD
AV
GND
Rev. A | Page 18 of 28
AD7798/AD7799
DD
IN-AMP
INTERNAL
CLOCK
–100
–100
ADC
Σ-Δ
–20
–40
–60
–80
–20
–40
–60
–80
0
0
0
0
Figure 12. Filter Profile with Update Rate = 4.17 Hz
Figure 13. Filter Profile with Update Rate = 16.7 Hz
20
20
REFERENCE
40
INTERFACE
DETECT
CONTROL
SERIAL
LOGIC
AND
60
40
FREQUENCY (Hz)
FREQUENCY (Hz)
80
100
60
DOUT/RDY
DIN
SCLK
CS
DV
DD
120
80
140
160
100
180
120
200