SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 18

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1.1
Table 8-3.
Note:
8.1.1.1
Table 8-4.
18
Address
0x0000 0000
Internal SRAM B (DCTM)
1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC
AT91SAM9261
Internal Memory Mapping
Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
Internal SRAM
Internal Memory Mapping
Internal SRAM Block Size
Internal SRAM C
Master 0: ARM926 Instruction
REMAP(RCB0) = 0
BMS = 1
Int. ROM
Table 8-3
status and the BMS state at reset.
The AT91SAM9261 embeds a high-speed 160 Kbyte SRAM. This Internal SRAM is split into
three areas. Its Memory Mapping is detailed in
Within the 160 Kbyte SRAM size available, the amount of memory assigned to each block is
software programmable as a multiple of 16 Kbytes according to
the size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal
SRAM B.
Note that among the ten 16 Kbyte blocks making up the Internal SRAM, two are permanently
assigned to Internal SRAM C.
At reset, the whole memory (160 Kbytes) is assigned to Internal SRAM C.
• Internal SRAM A is the ARM926EJ-S Instruction TCM and the user can map this SRAM
• Internal SRAM B is the ARM926EJ-S Data TCM and the user can map this SRAM block
• Internal SRAM C is only accessible by all the AHB Masters.
0
16 Kbytes
32 Kbytes
64 Kbytes
block anywhere in the ARM926 instruction memory space using CP15 instructions. This
SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through
the AHB bus at address 0x0010 0000.
anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0020 0000.
After reset and until the Remap Command is performed, this SRAM block is accessible
through the AHB bus at address 0x0030 0000 by all the AHB Masters.
After Remap, this SRAM block also becomes accessible through the AHB bus at address
0x0 by the ARM926 Instruction and the ARM926 Data Masters.
BMS = 0
EBI NCS0
summarizes the Internal Memory Mapping for each Master, depending on the Remap
(1)
Int. RAM C
REMAP (RCB0) = 1
160 Kbytes
144 Kbytes
128 Kbytes
96 Kbytes
0
144 Kbytes
128 Kbytes
112 Kbytes
16 Kbytes
80 Kbytes
Master 1: ARM926 Data
REMAP (RCB1) = 0
BMS = 1
Int. ROM
Table 8-3
Internal SRAM A (ITCM)
above.
BMS = 0
EBI NCS0
128 Kbytes
112 Kbytes
32 Kbytes
96 Kbytes
64 Kbytes
Table
(1)
8-4. This table provides
6062LS–ATARM–23-Mar-09
REMAP (RCB1) = 1
Int. RAM C
64 Kbytes
96 Kbytes
80 Kbytes
64 Kbytes
32 Kbytes