SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 17

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1
6062LS–ATARM–23-Mar-09
Embedded Memories
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to
8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7.
The area 0 is reserved for the addressing of the internal memories, and a second level of decod-
ing provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and
provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
The Bus Matrix manages five Masters and five Slaves.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master.
Regarding Master 0 and Master 1 (ARM926
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to
Table 8-1.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave.
Table 8-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• 32 KB ROM
• 160 KB Fast SRAM
– Single Cycle Access at full bus speed
– Single Cycle Access at full bus speed
– Supports ARM926EJ-S TCM interface at full processor speed
List of Bus Matrix Masters
List of Bus Matrix Slaves
Table 8-3
for details.
™
Instruction and Data), three different Slaves are
ARM926 Data
PDC
LCD Controller
USB Host
ARM926 Instruction
Internal SRAM
Internal ROM
LCD Controller and USB Host Port Interfaces
External Bus Interface
Internal Peripherals
AT91SAM9261
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