SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 14

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.2
7.3
14
Debug and Test Features
Bus Matrix
AT91SAM9261
• Integrated Embedded In-circuit Emulator Real-Time
• Debug Unit
• Embedded Trace Macrocell: ETM9
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
• Five Masters and Five Slaves handled
• One Address Decoder Provided per Master
• Boot Mode Select Option
• Remap Command
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
– Medium+ Level Implementation
– Half-rate Clock Mode
– Four Pairs of Address Comparators
– Two Data Comparators
– Eight Memory Map Decoder Inputs
– Two 16-bit Counters
– One 3-stage Sequencer
– One 45-byte FIFO
– Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the
– Round-Robin Arbitration (three modes supported: no default master, last accessed
– Burst Breaking with Slot Cycle Limit
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be Internal or External.
– Selection is made by BMS pin sampled at reset.
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD
Controller and USB Host Port.
default master, fixed default master)
internal boot, one for external boot, one after remap.
™
6062LS–ATARM–23-Mar-09