ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 45

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ATxmega256A3B

Manufacturer Part Number
ATxmega256A3B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega256A3B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
49
Usb Speed
No
Usb Interface
No
Spi
8
Twi (i2c)
2
Uart
6
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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4.20.8
8077H–AVR–12/09
AWEXLOCK – Advanced Waveform Extension Lock Register
tected by the Configuration Change Protection mechanism, for details refer to
”Configuration Change Protection” on page
• Bit 7:3 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2 - AWEXELOCK: Advanced Waveform Extension Lock for TCE0
Setting this bit will lock all registers in the AWEXE module for Timer/Counter E0 for further mod-
ifications. This bit is protected by the Configuration Change Protection mechanism, for details
refer to
• Bit 1 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 0 - AWEXCLOCK: Advanced Waveform Extension Lock for TCC0
Setting this bit will lock all registers in the AWEXC module for Timer/Counter C0 for further mod-
ifications. This bit is protected by the Configuration Change Protection mechanism, for details
refer to
Bit
+0x09
Read/Write
Initial Value
Section 3.12 ”Configuration Change Protection” on page
Section 3.12 ”Configuration Change Protection” on page
R
7
0
R
6
0
R
5
0
R
4
0
12.
R
3
0
AWEXELOCK
R/W
2
0
12.
12.
1
R
0
AWEXCLOCK
R/W
0
0
XMEGA A
Section 3.12
AWEX_LOCK
45

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