ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 130
ATxmega256A3B
Manufacturer Part Number
ATxmega256A3B
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega256A3B
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
49
Usb Speed
No
Usb Interface
No
Spi
8
Twi (i2c)
2
Uart
6
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATxmega256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega256A3BU-AU
Manufacturer:
ST
Quantity:
12 000
Company:
Part Number:
ATxmega256A3BU-MH
Manufacturer:
AAT
Quantity:
400
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13.3
8077H–AVR–12/09
Using the I/O Pin
Figure 13-1. General I/O pin functionality.
Use of an I/O pin is controlled from the user software. Each port has one Data Direction (DIR),
Data Output Value (OUT) that is used for port pin control. The Data Input Value (IN) register is
used for reading the port pins. In addition each pin has a Pin Configuration (PINnCTRL) register
for additional pin configuration.
Direction of the pin is decided by the DIRn bit in the DIR register. If DIRn is written to one, pin n
is configured as an output pin. If DIRn is written to zero, pin n is configured as an input pin.
When direction is set as output, the OUTn bit in OUT is used to set the value of the pin. If OUTn
is written to one, pin n is driven high. If OUTn is written to zero, pin n is driven low.
The IN register is used for reading the pin value. The pin value can always be read regardless of
the pin being configured as input or output, except if digital input is disabled.
I/O pins are tri-stated when reset condition becomes active, even if no clocks are running.
PINnCTRL
D
D
D
Q
OUTn
DIRn
INn
R
R
R
R
Synchronizer
Analog Input/Output
Q
Q
Q
D
Digital Input Pin
Q
R
D
Pull Enable
Pull Keep
Pull Direction
Input Disable
Wired AND/OR
Slew Rate Limit
Inverted I/O
XMEGA A
Pxn
130
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