ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 107

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.4.3
9.4.4
8077H–AVR–12/09
External reset
Watchdog reset
The BODACT fuse determines the BOD setting for active mode and idle mode, while the
BODPD fuse determines the brown-out detection setting for all sleep modes except idle mode.
Table 9-3.
The External reset circuit is connected to the external RESET pin. The external reset will trigger
when the RESET pin is driven below the RESET pin threshold voltage, V
minimum pulse period t
includes an internal pull-up resistor.
Figure 9-5.
For characterization data on V
sheet.
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. If the
WDT is not reset from the software within a programmable timout period, a Watchdog reset will
be given. The Watchdog reset is active for 1-2 clock cycles on the 2 MHz internal RC oscillator.
• Sampled: In this mode the BOD circuit will sample the VCC level with a period identical to
the 1 kHz output from the Ultra Low Power (ULP) oscillator. Between each sample the BOD is
turned off. This mode will reduce the power consumption compared to the enabled mode, but
a fall in the V
If a brown-out is detected in this mode, the BOD circuit is set in enabled mode to ensure that
the device is kept in reset until V
CC
BOD setting Fuse Decoding
External reset characteristics.
CC
level between 2 positive edges of the 1 kHz ULP output will not be detected.
BODACT[1:0]/ BODPD[1:0]
EXT
. The reset will be held as long as the pin is kept low. The reset pin
RST
00
01
10
11
and t
CC
is above V
EXT
and pull-up resistor values consult the device data
BOT
again.
RST
, for longer than the
XMEGA A
Reserved
Sampled
Disabled
Enabled
Mode
107