AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 82

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

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AT89LP428/828
Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-
trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next
clock phase. RECEIVE enables Shift Clock to alternate output function line of P3.1. As data bits
come in from the right, “1”s shift out to the left. When the “0” that was initially loaded into the
right-most position arrives at the left-most position in the shift register, it flags the RX Control
block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.
The relationship between the shift clock and data is determined by the combination of the SM2
and SMOD1 bits as listed in
idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the
output data is stable for both edges of the clock, or just one.
Table 16-5.
SM2
0
0
1
1
SMOD1
Mode 0 Clock and Data Modes
0
1
0
1
Clock Idle
High
High
Low
Low
Table 16-5
and shown in
Negative edge of clock
Negative edge of clock
While clock is high
While clock is low
Data Changed
Figure
16-2. The SM2 bit determines the
Negative edge of clock
Positive edge of clock
Positive edge of clock
Positive edge of clock
Data Sampled
3654A–MICRO–8/09