AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 116

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

23.2
116
Memory Organization
AT89LP428/828
The Programming Interface is the only means of externally programming the AT89LP428/828
microcontroller. The Interface can be used to program the device both in-system and in a stand-
alone serial programmer. The Interface does not require any clock other than SCK and is not
limited by the system clock frequency. During Programming, the system clock source of the tar-
get device can operate normally.
When designing a system where In-System Programming will be used, the following observa-
tions must be considered for correct operation:
The AT89LP428/828 offers 4K/8K bytes of In-System Programmable (ISP) nonvolatile Flash
code memory and 512/1024 bytes of nonvolatile Flash data memory. In addition, the device con-
tains a 128-byte User Signature Array and a 64-byte read-only Atmel Signature Array. The
memory organization is shown in
into pages of 64 bytes each. A single read or write command may only access a single page in
the memory. Each memory type resides in its own address space and is accessed by com-
mands specific to that memory. However, all memory types share the same page size.
User configuration fuses are mapped as a row in the memory, with each byte representing one
fuse. From a programming standpoint, fuses are treated the same as normal code bytes except
they are not affected by Chip Erase. Fuses can be enabled at any time by writing 00h to the
appropriate locations in the fuse row. However, to disable a fuse, i.e. set it to FFh, the entire
fuse row must be erased and then reprogrammed. The programmer should read the state of all
the fuses into a temporary location, modify those fuses which need to be disabled, then issue a
Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a simi-
lar manner to fuses except they may only be erased (unlocked) by Chip Erase.
Table 23-1.
• The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a
• The AT89LP428/828 will enter programming mode only when its reset line (RST) is
• The RST input may be disabled to gain an extra I/O pin. In these cases, the RST pin will
• The SS pin should not be left floating during reset if ISP is enabled.
• The ISP Enable Fuse must be set to allow programming during any reset period. If the ISP
• For standalone programmers, RST may be tied directly to GND to ensure correct entry into
maximum frequency of 5 MHz.
active (low). To simplify this operation, it is recommended that the target reset can be
controlled by the In-System programmer. To avoid problems, the In-System programmer
should be able to keep the entire target system reset for the duration of the programming
cycle. The target system should never attempt to drive the four SPI lines while reset is active.
always function as a reset during power up. To enter programming the RST pin must be
driven low prior to the end of Power-on Reset (POR). After POR has completed, the device
will remain in ISP mode until RST is brought high. Once the initial ISP session has ended, the
power to the target device must be cycled OFF and ON to enter another session.
Fuse is disabled, ISP may only be entered at POR.
Programming mode regardless of the device settings.
AT89LP428
AT89LP828
Device #
Code Memory Size
Code Size
4K bytes
8K bytes
Tables 23-1 and 23-2
Page Size
64 bytes
64 bytes
and
# Pages
Figure
128
64
23-2. The memory is divided
Address Range
0000H - 0FFFH
0000H - 1FFFH
3654A–MICRO–8/09