AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 10

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

3.2
3.2.1
3.2.2
3.2.3
10
Internal Data Memory
AT89LP428/828
DATA
IDATA
SFR
In order to read from the signature arrays, the SIGEN bit (DPCF.3) must be set. While SIGEN is
one, MOVC A,@A+DPTR will access the signature arrays. The User Signature Array is mapped
from addresses 0080H to 00FFH and the Atmel Signature Array is mapped from addresses
0000H to 003FH. SIGEN must be cleared before using MOVC to access the code memory. The
User Signature Array may also be modified by the In-Application Programming interface. When
IAP = 1 and SIGEN = 1, MOVX @DPTR instructions will access the array.
The AT89LP428/828 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O
memory mapped into a single 8-bit address space. Access to the internal data memory does not
require any configuration. The internal data memory has three address spaces: DATA, IDATA
and SFR; as shown in
Figure 3-2.
The first 128 bytes of RAM are directly addressable by an 8-bit address (00H - 7FH) included in
the instruction. The lowest 32 bytes of DATA memory are grouped into 4 banks of 8 registers
each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instruc-
tions using register addressing will only access the currently specified bank.
The full 256 bytes of internal RAM can be indirectly addressed using the 8-bit pointers R0 and
R1. The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in
the IDATA space.
The upper 128 direct addresses (80H - FFH) access the I/O registers. I/O registers on AT89LP
devices are referred to as Special Function Registers. The SFRs can only be accessed through
direct addressing. All SFR locations are not implemented.
page 15.
Lower
Upper
128
128
FFH
7F H
80H
0
Internal Data Memory Map
Indirect Addressing
DATA/IDATA
by Direct and
Accessible
Addressing
Accessible
Figure
by Indirect
IDATA
Only
Only
3-2.
Addressing
Accessible
by Direct
SFR
Special
Function
Registers
See “Special Function Registers” on
FFH
80H
Status and Control Bits
Ports
Timers
Registers
Stack Pointer
Accumulator
(Etc.)
3654A–MICRO–8/09