AT80C51RD2 Atmel Corporation, AT80C51RD2 Datasheet - Page 37

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AT80C51RD2

Manufacturer Part Number
AT80C51RD2
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT80C51RD2

Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Sram (kbytes)
1.25
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Watchdog
Yes

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11.2.3
11.3
4113D–8051–01/09
Baud Rate Selection for UART for Mode 1 and 3
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
Table 11-1.
Reset Value = 0000 0000b
Not bit addressable
Table 11-2.
SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit addressable
The Baud Rate Generator for transmit and receive clocks can be selected separately via the
T2CON and BDRCON registers.
Figure 11-4. Baud Rate selection
7
7
TIMER1
SADEN Register
SADEN - Slave Address Mask Register (B9h)
SADDR Register
TIMER2
TIMER1
TI MER2
INT_BRG
INT_BRG
6
6
5
5
RCLK
TCLK
0
1
0
1
4
4
TI MER_BRG_RX
TIMER_BRG_TX
3
3
RBCK
TBCK
0
1
0
1
2
2
AT80C51RD2
/ 16
/ 16
1
1
Rx Clock
Tx Clock
0
0
37

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