AT80C51RD2 Atmel Corporation, AT80C51RD2 Datasheet
AT80C51RD2
Manufacturer Part Number
AT80C51RD2
Description
Manufacturer
Atmel Corporation
Specifications of AT80C51RD2
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Sram (kbytes)
1.25
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Watchdog
Yes
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Active Errata List
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Errata History
Errata Descriptions
1. During UART Reception, Clearing REN May Generate Unexpected IT
2. SPI Interface - Transmission on Master Mode
3. SPI Interface - SPI SS pin Limitation on Master/Slave
4. SPI - SPI Slave Responding in a Multislave Configuration When Not
A
Rev
During UART Reception, Clearing REN May Generate Unexpected IT
SPI Interface - Transmission on Master Mode
SPI Interface - SPI SS pin Limitation on Master/Slave
SPI - SPI Slave Responding in a Multislave Configuration When Not Selected by the
Master and its SPDAT Register Loaded
SPI - SPI Slave Not Responding When Selected and Not Loaded
ALE Disabled Toggles During Internal MOVX
Timer 2 - Baud Rate Generator - No IT When TF2 is Set by Software
Timer 2 - Baud Rate Generator - Long Start Time
SPI Slave Mode/Data Corrupted
32 kHz Oscillator for AT83C51IC2/T80C51ID2 Needs External Feed Back Resistor
RB8 Lost With JBC on SCON
C51 Core – Bad Exit of Power-down in X2 Mode
During UART reception, if the REN bit is cleared between a start bit detection and
the end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine just after CLR RI, and run the Inter-
rupt routine code only if REN is set.
A 9th bit is transmitted by the interface when the clock rate is set on divide by 2
mode and a positive polarity is selected; the SPR2, SPR1, SPR0 bits are cleared
(000) and CPOL = 1 on the SPCON register.
Workaround
Set the clock rate divide by 4 and X2 mode.
The SS pin of the SPI does not return to an I/O when a One-to-One Master/Slave
intercommunication is performed.
Workaround
No
Selected by the Master and its SPDAT Register Loaded
In a multislave configuration, if the master is sending the Sck and the Tx data to all
the slaves, and only one slave is selected, the non-selected slaves respond and
generate the end of the transmission interruption (SPIF) if their SPDAT registers
are loaded before the transmission.
Workaround
No
above 00395
Lot Number
Nov 2001
1st Prod.
Trouble List
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
80C51 MCUs
AT83C51RB2
AT83C51RC2
AT83C51IC2
AT80C51ID2
AT80C51RD2
Errata Sheet
4242B–8051–03/08
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AT80C51RD2 Summary of contents
Page 1
... SPDAT registers are loaded before the transmission. Workaround No Trouble List 10, 11 80C51 MCUs AT83C51RB2 AT83C51RC2 AT83C51IC2 AT80C51ID2 AT80C51RD2 Errata Sheet 4242B–8051–03/08 ...
Page 2
SPI - SPI Slave Not Responding When Selected and Not Loaded SPI Slave does not respond when selected by a Master and no Data is loaded to be transmitted data is regis- tered and no SPIF interruption ...
Page 3
C51 Core Bad Exit of Power-down in X2 Mode – When exiting power-down mode by interrupt while CPU mode, it leads to bad execution of the first instruction run when CPU restarts. Workaround Set the CPU ...
Page 4
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...