AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 11

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7745C–AVR32–05/09
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From the application point of view, if all the rules described in this document are followed, the
state of the MCU when the application begins to execute at 80002000h will be the same as after
the last MCU hardware reset that occurred (whatever its causes) except that:
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If the ISP_FORCE GP fuse bit is 0 and the user has set the ISP_IO_COND_EN GP fuse bit
to 0, the ISP will no longer be reachable, except if the programmed application sets the
ISP_FORCE GP fuse bit to 1.
If the ISP_IO_COND_EN GP fuse bit is 1, but the bootloader configuration word is corrupted
(wrong CRC8) or has an invalid boot key or GPIO pin, the USB DFU ISP is systematically
launched to allow the user to correct this value.
Figure 6-2 mentions the ISP RAM key. It is a specific value written in the first word of the
INTRAM by the bootloader. This key is manipulated only by the boot process for its internal
behavior to know whether it is a warm boot following the execution of the USB DFU ISP. All
the user has to know about this key is that setting the first word of the INTRAM to
4953504Bh (“ISPK”) will alter the behavior of the bootloader after a subsequent reset, so it is
recommended that applications leave the first word of the INTRAM unused thanks to an
appropriate linker script (the C99 standard requires that a null pointer compares unequal to
a pointer to any object or function).
See the AVR UC3 datasheets referred to by Section 3 for a detailed description of the MCU
reset causes.
The Cycle Counter system register will have counted a few cycles.
The Brown-Out Detector may be activated, according to Figure 6-2.
The Power Manager registers may indicate some activity for Osc0 or PLL0 if the application
is launched from the ISP without reset.
The USB register bit-fields that are not reset when disabling the USB macro may not contain
their respective reset values if the application is launched from the ISP without reset.
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