AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 10

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10
Flash and ISP specification
Figure 6-2. Boot Process
Note:
•
The ISP_FORCE GP fuse bit is set to 1 by the ISP on each ISP command received and it is
set to 0 by the ISP when a request to start the application is received. That means that after
a command has been sent using BatchISP, the user will not be able to start his application
until he has issued a START operation to BatchISP. This behavior ensures the consistency
of programmed data thanks to a non-volatile programming session.
WDT Reset
Yes
ISP_FORCE=1 on DFU
Set ISP RAM Key
(@ 80000000h)
ISP_FORCE=0
Start Customer
Disable WDT
Requested?
Application?
Bootloader
Reset
Yes
No
Yes
No
No
Yes
ISP I/O Condition Active?
ISP User Page Cfg OK?
POR or EXT or OCD or
Enable BOD with reset
ISP_IO_COND_EN=1?
(CRC8, Boot Key, Pin)
JTAG or JTAG HW?
ISP_BOD_EN=1?
ISP_FORCE=1?
(@ 80000000h)
Reset Cause:
Reset Vector
Yes
Yes
Yes
Yes
No
Jump
No
No
No
Note:
ISP_BOD_EN is GP fuse bit 29.
ISP_IO_COND_EN is GP fuse bit 30.
ISP_FORCE is GP fuse bit 31.
No
Yes
Reset Cause:
ISP RAM Key
WDT?
Set?
SW Reset CPU Regs
Customer Application
Clear ISP RAM Key
(@ 80002000h)
ISP RAM Key
Disable WDT
No
Set?
No
Yes
Yes
7745C–AVR32–05/09
No