SC16C852LIB,157 NXP Semiconductors, SC16C852LIB,157 Datasheet - Page 37

IC UART DUAL W/FIFO 48-LQFP

SC16C852LIB,157

Manufacturer Part Number
SC16C852LIB,157
Description
IC UART DUAL W/FIFO 48-LQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C852LIB,157

Features
Programmable
Number Of Channels
2, DUART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
1.8V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935283098157
SC16C852LIB
SC16C852LIB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C852LIB,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C852L
Product data sheet
7.15 Transmit Interrupt Level register (TXINTLVL)
7.16 Receive Interrupt Level register (RXINTLVL)
Table 26.
[1]
This 8-bit register is used to store the transmit FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1.
Table 27.
[1]
This 8-bit register is used to store the receive FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1.
Table 28.
Cont-3
0
1
0
1
X
X
X
1
0
1
Bit
7:0
Bit
7:0
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
For 32-byte FIFO mode, refer to
Table 27
Table 28
Symbol
TXINTLVL[7:0]
Symbol
RXINTLVL[7:0]
Cont-2
0
0
1
1
X
X
X
0
1
1
Software flow control functions
TXINTLVL register bits description
RXINTLVL register bits description
shows TXINTLVL register bit settings.
shows RXINTLVL register bit settings.
All information provided in this document is subject to legal disclaimers.
Cont-1
X
X
X
X
0
1
0
1
1
1
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 4 — 1 February 2011
Description
This register stores the programmable transmit interrupt trigger levels
for 128-byte FIFO mode
Description
This register stores the programmable receive interrupt trigger levels
for 128-byte FIFO mode
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Cont-0
X
X
X
X
0
0
1
1
1
1
Section
7.3.
TX, RX software flow controls
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
[1]
[1]
[1]
.
.
SC16C852L
© NXP B.V. 2011. All rights reserved.
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