SC16C852LIB,157 NXP Semiconductors, SC16C852LIB,157 Datasheet - Page 29

• Manufacturer Part Number: SC16C852LIB,157
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C852LIB,157

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283098157; SC16C852LIB; SC16C852LIB

NXP Semiconductors
SC16C852L
Product data sheet
Table 12.
[1]
[2]
Table 13.
[1]
Table 14.
[1]
Bit
3
(cont.)
2
1
0
FCR[7]
0
0
1
1
FCR[5]
0
0
1
1
For 128-byte FIFO mode, refer to
For 128-byte FIFO mode, refer to
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
Symbol
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
RCVR trigger levels
TX FIFO trigger levels
FCR[6]
0
1
0
1
FCR[4]
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
Transmit operation in mode ‘1’: When the SC16C852L is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYA/TXRDYB pin will be a
logic 1 when the transmit FIFO is completely full; see
operation”. It will be a logic 0 when the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C852L is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDYA/RXRDYB pin will go to a
logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Rev. 4 — 1 February 2011
RX FIFO trigger level (bytes) in 32-byte FIFO mode
8
16
24
28
TX FIFO trigger level (bytes) in 32-byte FIFO mode
16
8
24
30
Section
Section
7.16,
7.15,
Section
Section
…continued
7.17,
7.17,
Section
Section
7.18.
7.18.
Section 6.4 “FIFO
Section 6.4 “FIFO
SC16C852L
Section 6.10 “DMA
© NXP B.V. 2011. All rights reserved.
operation”).
operation”).
[1]
[1]
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