SC28L92A1A,512 NXP Semiconductors, SC28L92A1A,512 Datasheet - Page 12

• Manufacturer Part Number: SC28L92A1A,512
• Description: IC UART DUAL W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L92A1A,512

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935263293512; SC28L92A1A; SC28L92A1A

NXP Semiconductors
Table 3.
SC28L92_7
Product data sheet
Symbol
INTRN
X1/CLK
X2
RxDA
RxDB
TxDA
TxDB
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
Pin
PLCC44 QFP44 HVQFN48
24
36
37
35
11
33
13
32
14
31
15
30
16
29
17
8
5
40
Pin description for 68xxx bus interface (Motorola)
18
30
31
29
5
28
6
27
7
26
8
25
9
24
10
2
43
34
19
32
33
31
5
30
8
29
9
28
10
27
11
26
12
2
47
38
Type
O
I
O
I
I
O
O
O
O
O
O
O
O
O
O
I
I
I
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Description
Interrupt request: Active LOW, open-drain, output which signals the
CPU that one or more of the eight maskable interrupting conditions
are true. This pin requires a pull-up.
Crystal 1: Crystal or external clock input. A crystal or clock of the
specified limits must be supplied at all times. When a crystal is used, a
capacitor must be connected from this pin to ground (see
Crystal 2: Connection for other side of the crystal. When a crystal is
used, a capacitor must be connected from this pin to ground (see
Figure
be left open.
Channel A receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram
Channel B receiver serial data input: The least significant bit is
received first. See note on drive levels at block diagram
Channel A transmitter serial data output: The least significant bit is
transmitted first. This output is held in the ‘mark condition when the
transmitter is disabled, idle or when operating in local loopback mode.
See note on drive levels at block diagram
Channel B transmitter serial data output: The least significant bit is
transmitted first. This output is held in the Mark condition when the
transmitter is disabled, idle, or when operating in local loopback mode.
See note on drive levels at block diagram
Output 0: General purpose output or channel A request to send
(RTSAN, active LOW). Can be deactivated automatically on receive or
transmit.
Output 1: General purpose output or channel B request to send
(RTSBN, active LOW). Can be deactivated automatically on receive or
transmit.
Output 2: General purpose output, or channel A transmitter 1 or 16
clock output, or channel A receiver 1 clock output.
Output 3: General purpose output or open-drain, active LOW
counter/timer output or channel B transmitter 1 clock output, or
channel B receiver 1 clock output.
Output 4: General purpose output or channel A open-drain, active
LOW, RxA interrupt ISR [1] output.
Output 5: General purpose output or channel B open-drain, active
LOW, RxB interrupt ISR[5] output.
Output 6: General purpose output or channel A open-drain, active
LOW, TxA interrupt ISR[0] output.
Output 7: General purpose output, or channel B open-drain, active
LOW, TxB interrupt ISR[4] output.
Input 0: General purpose input or channel A clear to send active LOW
input (CTSAN).
Input 1: General purpose input or channel B clear to send active LOW
input (CTSBN).
Input 2: General purpose input or counter/timer external clock input.
17). If X1/CLK is driven from an external source, this pin must
…continued
(Figure
(Figure
2).
2).
SC28L92
© NXP B.V. 2007. All rights reserved.
(Figure
(Figure
Figure
12 of 73
2).
2).
17).