PEB20320H-V34 Infineon Technologies, PEB20320H-V34 Datasheet - Page 184
PEB20320H-V34
Manufacturer Part Number
PEB20320H-V34
Description
IC CONTROLR 32-CH HDLC 160-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB20320H-V34.pdf
(252 pages)
Specifications of PEB20320H-V34
Function
Multichannel Network Interface Controller (MUNICH)
Interface
HDLC, V.110, X.30
Voltage - Supply
5V
Current - Supply
100mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-BSQFP
Includes
Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-
Number Of Circuits
-
Other names
PEB20320H-V34
PEB20320H-V34IN
PEB20320H-V34IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB20320H-V34
Manufacturer:
Infineon Technologies
Quantity:
10 000
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User’s Manual
Application Specific Hardware
The application specific hardware consists of an ISDN primary rate interface and an
Ethernet interface. The MUNICH32 PEB 20320 in conjunction with the layer 1 SIEMENS
components ACFA (Advanced CMOS Frame Aligner) PEB 2035 and PRACT (Primary
Rate Access Clock Generator and Transceiver) PEB 22320 are used to build the primary
rate interface. Incoming data from the ISDN is first processed from the PRACT. It
translates the HDB3 coded line signals in dual rail signals. The PRACT also supplies
ACFA and MUNICH32 with clock signals. Main task of the ACFA is the frame alignment.
Besides, the ACFA translates the dual rail data in a single rail, unipolar bit stream which
can be processed by the MUNICH32.
The MUNICH32 handles up to 32 channels of a full duplex PCM highway. All time-slots
may have data rates between 8 Kbit/s and 64 Kbit/s. The MUNICH32 supports besides
other protocols the HDLC formatting/deformatting. If programmed for HDLC mode, the
MUNICH32 performs HDLC specific functions like framing, CRC check/generation,
flag stuffing and zero bit insertion/deletion autonomously. An on-chip 64-channel
DMA controller allows the device to store/read data into/from the SRAM. The DMA
controller manages long word or word transfers via a 32-bit processor interface. The
Figure 87
ISDN Interface
The Ethemet interface is built with a LAN controller, a Manchester encoder/decoder and
a transceiver. The LAN controller supports all IEEE 802.3 standards. The Ethernet
framing: preamble generation, source address generation, destination address
checking, short-frame detection, automatic length field handling is performed. After
LAN controller processing the transmit data is Manchester encoded and forwarded to the
transmission line, while receive data is Manchester decoded before being processed by
the LAN controller.
P interface can be configured to be Motorola 68020 or intel 80386 compatible.
P Interface
MUNICH32
PCM
Highway
ACFA
184
Dual Rail
Unipolar
Signals
PRACT
Overvoltage
Application Notes
PEB 20320
Line IN
Line OUT
ITS08285
01.2000
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