PEB20320H-V34 Infineon Technologies, PEB20320H-V34 Datasheet - Page 168

• Manufacturer Part Number: PEB20320H-V34
• Description: IC CONTROLR 32-CH HDLC 160-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB20320H-V34

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, V.110, X.30
• Voltage - Supply: 5V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BSQFP
• Includes: Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20320H-V34; PEB20320H-V34IN

User’s Manual
4.4
The receive descriptor contains 4 long words; the first, third and fourth have to be written
by the CPU, the second is written by the MUNICH32 when it branches to the next receive
descriptor or when it starts polling the HOLD bit.
Note: The MUNICH32 branches to a next descriptor without writing the second long
HOLD:
FE
31
15
0
0
HOLD
word if the receive initialization command is used during normal operation (see
Chapter 4.2.4)
14
30
0
Receive Descriptor
C
Setting the HOLD bit by the host prevents the device from branching to the
next descriptor. The current data section is still filled.
– Afterwards the second descriptor long word is written by the MUNICH32.
– Afterwards the device starts polling the HOLD bit, received data, and
– When HOLD = 0 is polled
13
For HDLC, TMB, TMR the FE and C-bit is set. If the frame could not
completely be stored into the data section the RA bit is set in the status.
An interrupt with set FI bit is generated, and in case the frame was aborted,
the ERR bit is also set.
For TMA, V.110/X.30 the C-bit and the RA bit is set and an interrupt with
set ERR but with FI = 0 is generated.
received events normally leading to interrupts (with RT = 1) are discarded
until HOLD = 0 is polled. Each 1 … 4 byte data word or interrupt event
normally leading to an access now results in a poll cycle.
Whenever HOLD = 1 is polled the next receive descriptor address is read
but ignored.
• for HDLC, TMB, TMR the device continues to discard data until the end
0
of a received frame or an event leading to an interrupt (with RT = 1) is
29
HI
0
12
Status
0
28
11
0
27
Next Receive Descriptor Pointer
Next Receive Descriptor Pointer
10
0
26
Receive Data Pointer
Receive Data Pointer
9
0
25
8
0
24
168
7
0
0
23
BNO
6
0
0
NO
22
Detailed Register Description
5
0
0
21
20
4
0
0
19
3
0
0
18
2
0
0
PEB 20320
17
1
0
0
01.2000
16
0
0
0