DS2151QB Maxim Integrated Products, DS2151QB Datasheet - Page 34

• Manufacturer Part Number: DS2151QB
• Description: IC TXRX T1 1-CHIP 5V LP 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2151QB

• Function: Single-Chip Transceiver
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 65mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Includes: Alarm Detector and Generator, CSU Loop Codes Generator and Detector, DSX-1 and CSU Line Build-Outs Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

9 TRANSMIT TRANSPARENCY AND IDLE REGISTERS
There is a set of seven registers in the DS2151Q that can be used to custom tailor the data that is to be
transmitted onto the T1 line, on a channel-by-channel basis. Each of the 24 T1 channels can be either
forced to be transparent or to have a user defined idle code inserted into them. Each of these special
registers is defined below.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (Address = 39
to 3B Hex)
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no Robbed-Bit signaling will be inserted nor will the channel
have Bit 7 stuffing performed. However, in the D4 framing mode, Bit 2 will be overwritten by a 0 when a
Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from determining
which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all
24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are
programmed. In this manner, the TTR registers are only affecting which channels are to have Robbed-Bit
signaling inserted into them. See
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address = 3C to 3E Hex)
(MSB)
(MSB)
CH16
CH24
CH16
CH24
CH8
CH8
SYMBOL
SYMBOL
CH24
CH24
CH1
CH1
CH15
CH23
CH7
CH15
CH23
CH7
CH14
CH22
CH6
CH14
CH22
CH6
POSITION
POSITION
TTR3.7
TTR1.0
TIR3.7
TIR1.0
Figure 14-9
CH13
CH21
CH5
CH13
CH21
CH5
for more details.
NAME AND DESCRIPTION
Transmit Idle Registers.
0 = do not insert the Idle Code into this DS0 channel
1 = insert the Idle Code into this channel
NAME AND DESCRIPTION
Transmit Transparency Registers.
0 = this DS0 channel is not transparent
1 = this DS0 channel is transparent
CH12
CH20
CH4
CH12
CH20
34 of 60
CH4
CH11
CH19
CH3
CH11
CH19
CH3
CH10
CH18
CH2
CH10
CH18
CH2
(LSB)
CH17
CH1
CH9
(LSB)
CH17
CH1
CH9
TIR2 (3D)
TIR1 (3C)
TIR3 (3E)
TTR2 (3A)
TTR3 (3B)
TTR1 (39)