DS2151QB Maxim Integrated Products, DS2151QB Datasheet - Page 18

• Manufacturer Part Number: DS2151QB
• Description: IC TXRX T1 1-CHIP 5V LP 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2151QB

• Function: Single-Chip Transceiver
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 65mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Includes: Alarm Detector and Generator, CSU Loop Codes Generator and Detector, DSX-1 and CSU Line Build-Outs Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

4.5
When either the CCR3.1 or CCR3.2 bits are set to 1, the DS2151Q will replace the normal transmitted
payload with either the Loop Up or Loop Down code, respectively. The DS2151Q will overwrite the
repeating loop code pattern with the framing bits. The SCT will continue to transmit the loop codes as
long as either bit is set. It is an illegal state to have both CCR3.1 and CCR3.2 set to 1 at the same time.
4.6
The SCT always examines both the transmit and receive data streams for violations of the following rules
which are required by ANSI T1.403-199X:
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively.
When the CCR3.3 is set to 1, the DS2151Q will force the transmitted stream to meet this requirement no
matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to 0,
since B8ZS encoded data streams cannot violate the pulse density requirements.
4.7
On power-up, after the supplies are stable, the DS2151Q should be configured for operation by writing to
all of the internal registers (this includes setting the Test Register to 00Hex) since the contents of the
internal registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to
reset the line interface (it will take the DS2151Q about 40ms to recover from the LIRST being toggled).
Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 (this step can be
skipped if the elastic stores are disabled).
– no more than 15 consecutive 0s
– at least N 1s in each and every time window of 8 x (N +1) bits where N = 1 through 23
Loop Code Generation
Pulse Density Enforcer
Power-Up Sequence
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