DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 23

• Manufacturer Part Number: DS2156L+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2156L+

• Function: Single-Chip Transceiver
• Interface: E1, J1, T1, TDM, UTOPIA II
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

3.1.2 Receive Side
Signal Name:
Signal Description:
Signal Type:
T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a
frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.
Signal Name:
Signal Description:
Signal Type:
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
Signal Description:
Signal Type:
1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK
when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Useful for parallel-to-serial conversion of channel data.
Signal Name:
Signal Description:
Signal Type:
A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels.
Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the
receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN–PRI.
Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and
for per-channel conditioning. See Section 17 for details.
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe
(IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.6, RSYNC can also be set to
output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin
can be enabled to be an input through IOCR1.4, at which a frame or multiframe boundary pulse is applied.
Signal Name:
Signal Description:
Signal Type:
An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries.
RLINK
Receive Link Data
Output
RLCLK
Receive Link Clock
Output
RCLK
Receive Clock
Output
RCHCLK
Receive Channel Clock
Output
RCHBLK
Receive Channel Block
Output
RSER
Receive Serial Data
Output
RSYNC
Receive Sync
Input/Output
RFSYNC
Receive Frame Sync
Output
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