MT48LC32M8A2P-7E:DTR Micron Technology Inc, MT48LC32M8A2P-7E:DTR Datasheet - Page 67
MT48LC32M8A2P-7E:DTR
Manufacturer Part Number
MT48LC32M8A2P-7E:DTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC32M8A2P-7EDTR.pdf
(87 pages)
Specifications of MT48LC32M8A2P-7E:DTR
Lead Free Status / Rohs Status
Compliant
- Current page: 67 of 87
- Download datasheet (4Mb)
Figure 38: WRITE – DQM Operation
Burst Read/Single Write
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
DQM
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Bank
T0
Row
Row
t CKH
t CMH
t AH
t AH
t AH
Note:
t RCD
t CK
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
T1
NOP
1. For this example, BL = 4.
Disable auto precharge
Enable auto precharge
t CMS
t CL
t DS
Column m
WRITE
T2
Bank
D
t CMH
IN
t DH
t CH
T3
NOP
67
t DS
T4
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
IN
t DH
t DS
256Mb: x4, x8, x16 SDRAM
T5
NOP
D
IN
t DH
© 1999 Micron Technology, Inc. All rights reserved.
NOP
T6
WRITE Operation
NOP
T7
Don’t Care
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