P87C554SBAA NXP Semiconductors, P87C554SBAA Datasheet - Page 66

• Manufacturer Part Number: P87C554SBAA
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C554SBAA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Ram Size: 512 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 7-chx10-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
V
other outputs unless otherwise specified.
2003 Jan 28
DD
External Program Memory
1/f
t
t
t
t
t
t
t
t
t
t
t
External Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Clock
t
t
t
t
UART Timing – Shift Register Mode
t
t
t
t
t
SYMBOL
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
CLK
and T
amb
minimum and maximum, per device specifications table; V
FIGURE
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
50, 51
49
49
49
49
49
49
49
49
49
49
49
49
51
52
52
52
52
53
53
53
53
53
System clock frequency, see Note 1
ALE pulse width
Address valid to ALE LOW
Address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN LOW to address float
RD pulse width
WR pulse width
RD LOW to valid data in
Data hold after RD
Data float after RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to RD or WR LOW
Address valid to RD low or WR LOW
Data valid to WR transition
Data hold after WR
Data valid time WR HIGH
RD LOW to address float
RD or WR HIGH to ALE HIGH
High time
Low time
Rise time
Fall time
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
PARAMETER
2
C, PWM, capture/compare,
66
SS
= 0 V; C
16 MHz CLOCK
48.75
43.75
88.75
179.5
37.5
6.25
6.25
6.25
87.5
87.5
1.25
6.25
6.25
33.3
33.3
32.5
MIN
500
50
–
–
0
–
–
–
–
0
–
–
–
–
–
–
0
–
L
= 100 pF for Port 0, ALE and PSEN; C
143.75
116.25
33.75
76.25
66.25
56.25
179.5
MAX
6.25
42.5
100
60
10
50
50
20
20
–
–
–
–
–
–
–
–
–
–
–
–
–
0
–
–
–
–
3.5 t
0.5 t
0.5 t
0.5 t
1.5 t
1.5 t
0.5 t
0.5 t
0.5 t
5 t
3 t
3 t
t
t
2 t
CLK
CLK
t
t
CLK
CLK
CLK
CLK
CLK
6 t
CLK
MIN
CLK
3.5
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
VARIABLE CLOCK
–
–
0
–
–
–
–
0
–
–
–
–
–
–
0
–
CLK
–25
–30
–100
–100
–133
–75
–130
0.4
0.4
–25
–25
–25
–45
–50
–30
–25
–25
4.5 t
0.5 t
1.5 t
0.5 t
2.5 t
2.5 t
1.5 t
4 t
5 t
t
t
2 t
CLK
CLK
t
CLK
CLK
CLK
80C554/87C554
MAX
CLK
CLK
CLK
CLK
CLK
CLK
CLK
16
10
20
20
CLK
–
–
–
–
–
–
–
–
–
–
–
–
–
0
–
–
–
–
–20
–150
–133
L
–65
–165
0.6
0.6
–60
–25
–80
–90
+50
+25
= 80 pF for all
Product data
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns