P87C554SBAA NXP Semiconductors, P87C554SBAA Datasheet - Page 35

• Manufacturer Part Number: P87C554SBAA
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C554SBAA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Ram Size: 512 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 7-chx10-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

Philips Semiconductors
A
In the master transmitter mode, the arbitration logic checks that
every transmitted logic 1 actually appears as a logic 1 on the I
bus. If another device on the bus overrules a logic 1 and pulls the
SDA line low, arbitration is lost, and SIO1 immediately changes from
master transmitter to slave receiver. SIO1 will continue to output
clock pulses (on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the master receiver mode. Loss of
arbitration in this mode can only occur while SIO1 is returning a “not
acknowledge: (logic 1) to the bus. Arbitration is lost when another
device on the bus pulls this signal LOW. Since this can occur only at
the end of a serial byte, SIO1 generates no further clock pulses.
Figure 36 shows the arbitration procedure.
2003 Jan 28
RBITRATION AND
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
SDA
SCL
SDA
SCL
1. Another device transmits identical serial data.
2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is
3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will
1. Another service pulls the SCL line low before the SIO1 “mark” duration is complete. The serial clock generator is immediately
2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state
3. The SCL line is released, and the serial clock generator commences with the mark duration.
lost, and SIO1 enters the slave receiver mode.
not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.
reset and commences with the “space” duration by pulling SCL low.
until the SCL line is released.
S
YNCHRONIZATION
DURATION
L
MARK
OGIC
1
(1)
(1)
Figure 37. Serial Clock Synchronization
Figure 36. Arbitration Procedure
2
(1)
SPACE DURATION
2
C
2
C, PWM, capture/compare,
3
35
(2)
The synchronization logic will synchronize the serial clock generator
with the clock pulses on the SCL line from another device. If two or
more master devices generate clock pulses, the “mark” duration is
determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the
longest “spaces.” Figure 37 shows the synchronization procedure.
A slave may stretch the space duration to slow down the bus
master. The space duration may also be stretched for handshaking
purposes. This can be done after each bit or after a complete byte
transfer. SIO1 will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been
transferred. The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
(2)
4
(3)
(3)
(1)
8
80C554/87C554
ACK
9
SU00967
SU00968
Product data