TXC02050AIPL Transwitch Corporation, TXC02050AIPL Datasheet

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... Error rate clock reference 6,8,34 Mbit/s transmit bipolar data Patents Pending Copyright 1994 TranSwitch Corporation TXC and TranSwitch are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 DESCRIPTION The TranSwitch Multi-rate Receive/Transmit (MRT) device is a CMOS VLSI device that provides the func- ...

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BLOCK DIAGRAM LINE SIDE EQB1 EQB0 LOW VAGC GNDA DI1 Equalization AGC Network DI2 LBKTX TPO Output Driver TNO VDD GND BLOCK DIAGRAM DESCRIPTION On the Line Side, a symmetrical bipolar signal is applied to the input signal pin (DI1), ...

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Two Terminal Side interfaces are provided, a positive and negative rail (RP and RN) or NRZ (RD) interface. The selection is determined by the state placed on the signal lead labeled PNENB. When a low is applied to the signal ...

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PIN DESCRIPTIONS Power Supply and Ground Symbol Pin No. I/O/P* VDD 10,18,35, 37,42 GND 1,6,11,16,32, 36,39,44 VAGC 23 GNDA 31 *Note Input Output Power Line Side I/O Symbol Pin No. I/O/P DI1 29 DI2 ...

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Symbol Pin No. I/O/P CLKO 15 CLKI 38 TP/ Alarm Signal Outputs Symbol Pin No. I/O/P TXLOC 2 LQLTY RXLOS 20 Type O CMOS8mA Clock Out: Receive clock output. Receive positive and negative rail ...

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MRT Control Leads Symbol Pin No. I/O/P RXAIS 3 BERCK 4 PNENB 8 DCK 9 RXDIS 21 LBKRX 24 LBKTX 25 LOW 26 LBKTX LBKRX Note 1: Setting and ports. Type I CMOSr Receive Alarm Indication Signal: When RXAIS is ...

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Symbol Pin No. I/O/P EQB1 27 EQB0 28 TXAIS 43 Pins With External Components Symbol Pin No. I/O/P VCOC 7 PLLC 17 AGFIL 22 Type I CMOSr Equalizer Bit 1: MSB of equalizer setting. I Equalizer Bit 0: LSB of ...

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ABSOLUTE MAXIMUM RATINGS* Parameter Supply voltage AGC Supply Voltage DC input voltage Continuous power dissipation Ambient operating temperature Operating junction temperature Storage temperature range *Note: Operating conditions exceeding those listed in Absolute Maximum Ratings may cause permanent failure. Exposure to ...

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INPUT, OUTPUT, AND I/O PARAMETERS Input Parameters For TTL Parameter Min V 2 Input leakage current Input capacitance Input Parameters For TTLr Parameter Min V 2 Input leakage current Input capacitance Note: Input has ...

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Output Parameters For TTL4mA Parameter Min 0 2.8 RISE t 1.3 FALL Output Parameters For TTL24mA Parameter Min 0 ...

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TIMING CHARACTERISTICS Detailed timing diagrams for the MRT are illustrated in Figures 3 through 9. All output times are measured with maximum load capacitance appropriate for the pin type. Timing parameters are measured )/2 as ...

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Figure 4. Pulse Mask at the 8448 kbit/s Interface V 2.370 1.185 0 Reference: CCITT Recommendation G.703 Figure 5. Pulse Mask at the 6312 kbit/s Interface Nominal pulse shape Coordinates of each point 2. ...

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Terminal Side Timing Characteristics CLKI 1.4V DATA TP,TD VALID Parameter CLKI clock period CLKI duty cycle ( PWH CYC TP,TD set-up time to CLKI TP,TD hold time after CLKI Note 1: CLKI symmetry is measured about the 1.4VDC ...

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CLKI 1.4V DATA TP ,TD VALID DATA TN VALID Parameter CLKI clock period CLKI duty cycle ( PWH CYC TP,TD & TN set-up time to CLKI TP,TD & TN hold time after CLKI Note 1: CLKI symmetry is ...

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OPERATION POWER SUPPLY Ferrite Bead Fair Rite 2743002111 23 VAGC A 31 GNDA A Figure 10. MRT Power Supply Connections The MRT device has separate power supply pins labeled VDD and VAGC. The VAGC supply pin is connected to the ...

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OVERVIEW Line Side Input Impedance The input impedance of the MRT is a function of the state of the LOW lead and the operating rate. Table 1 lists the input impedance of the MRT at the operating line rates (which ...

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Line Side Output Circuits Figure 12 illustrates the output circuit required for operating the MRT device for a 34368 kbit/s application. The transformer and resistors shown assure that the output waveform meets the CCITT mask for 34368 kbit/s transmission and ...

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Jitter Tolerance CCITT Recommendation G.823 specifies that network equipment must be able to accommodate and tolerate levels of jitter up to certain specified limits. The MRT accommodates and tolerates more input jitter than the level of input jitter specified by ...

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Maximum Output Jitter In Absence of Input Jitter CCITT Recommendation G.823 specifies that it is necessary to restrict the amount of jitter generated by indi- vidual equipments. The actual limits depend on the type of equipment (and application). In the ...

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PACKAGING The MRT device is packaged in a 44-pin plastic leaded chip carrier suitable for socket or surface mounting. All dimensions shown are in inches and are nominal unless otherwise noted. .650 (nom) SQ. .075 .500 (nom) SQ ...

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ORDERING INFORMATION Part Number: TXC-02050-AIPL RELATED PRODUCTS TXC-03701 E2/E3F Framer VLSI device. The E2/E3 Framer directly interfaces with the MRT and provides multi-mode framing for CCITT G.751/G.753 (34368 kbit/s) or CCITT G.742/ G.745 (8448 kbit/s) signals. TXC-03702 JT2F Framer VLSI ...

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STANDARDS DOCUMENTATION SOURCES Telecommunication technical standards and reference documentation may be obtain from the following organizations: ANSI (U.S.A.): American National Standards Institute (ANSI) 11 West 42nd Street New York, New York 10036 Tel: 212-642-4900 Fax: 212-302-1286 Bellcore (U.S.A.): Bellcore Attention ...

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LIST OF DATA SHEET CHANGES This change list identifies those areas within the updated MRT Data Sheet that have technical differences rel- ative to the superseded MRT Data Sheet: Updated MRT Data Sheet: Superseded MRT Data Sheet: The page numbers ...

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NOTES - - 24 - MRT TXC-02050-MB Ed. 3, April 1994 ...

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TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, soft- ...

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... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 • • Fax: 203-926-9453 www.transwitch.com ...