CYNSE70128-83BGI Cypress Semiconductor Corp, CYNSE70128-83BGI Datasheet - Page 73

• Manufacturer Part Number: CYNSE70128-83BGI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGI

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The logical 144-bit search operation is as shown in Figure 10-48. The entire table of 31 devices (consisting of 144-bit entries) is
compared against a 144-bit word K that is presented on the DQ bus in cycles A and B of the command using the GMR and local
mask bits. The GMR is the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the
command’s cycle A.
The 144-bit word K that is presented on the DQ bus in cycles A and B of the command is also stored in the even and odd
comparand registers specified by the Comparand Register Index in the command’s cycle B. In x144 configurations, the even and
odd comparand registers can subsequently be used by the Learn command in only the first non-full device.
command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one
block. The word K that is presented on the DQ bus in cycles A and B of the command is compared with each entry in the table
starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM
address on the SADR[23:0] lines (see ”SRAM Addressing” on page 105). The global winning device will drive the bus in a specific
cycle. On global miss cycles the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default
driving device for SSF and SSV signals) will be the default driver for such missed cycles.
bit-configured tables, the search hit will always be at an even address.
The Search command is a pipelined operation. It executes a search at half the rate of the frequency of CLK2X for 144-bit searches
in x144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search command cycle
(two CLK2X cycles) is shown in Table 10-24.
Table 10-24. The Latency of Search from Instruction to SRAM Access Cycle
The latency of a search from command to the SRAM access cycle is 6 for 1–31 devices in the table and where TLSZ = 10.
In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-25.
Table 10-25. Shift OF SSF and SSV from SADR
Document #: 38-02040 Rev. *F
• Cycle B: The host ASIC continues to drive the CMDV high and to apply Search command code (10) on CMD[1:0]. CMD[5:2]
must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles
A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 16 for the description of SSR[0:7]). The DQ[71:0] is driven with 72-bit data ([71:0])to be compared
against all odd locations.
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
000
001
010
011
Must be same in each of the 31
Will be same in each of the 31
Comparand Register (odd)
Comparand Register (even)
71
devices
devices
Max Table Size
256K × 144 bits
992K × 144 bits
32K × 144 bits
Figure 10-48. x144 Table with 31 Devices
A
B
0
1015806
Location
address
GMR
L
0
2
4
6
K
CFG = 0101010101010101
143
143
Number of CLK Cycles
(144-bit configuration)
Even
A
0
1
2
3
Odd
B
Latency in CLK Cycles
Note
0
0
. During 144-bit searches of 144-
(First matching entry)
4
5
6
CYNSE70128
Note
Page 73 of 137
. The Learn