CYNSE70128-83BGI Cypress Semiconductor Corp, CYNSE70128-83BGI Datasheet - Page 58

• Manufacturer Part Number: CYNSE70128-83BGI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGI

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The 144-bit word K (presented on the DQ bus in cycles A and B of the command) is also stored in the even and odd comparand
registers specified by the Comparand Register Index in the command’s cycle B. In x144 configurations, the even and odd
comparand registers can subsequently be used by the Learn command in only one of the devices (the first non-full device). The
word K (presented on the DQ bus in cycles A and B of the command) is compared to each entry in the table starting at location 0.
The first matching entry’s location, address L, is the winning address that is driven as part of the SRAM address on the SADR[23:0]
lines (see “SRAM Addressing” on page 105). The global winning device will drive the bus in a specific cycle. On global miss cycles
the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving device for SSF and
SSV signals) will be the default driver for such missed cycles.
search hit will always be at an even address.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 144-bit
searches in x144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-21.
Table 10-21. Search Latency from Instruction to SRAM Access Cycle
For one to eight devices in the table and TLSZ = 01, the latency of a Search from command to SRAM access cycle is 5. In addition,
SSV and SSF shift further to the right for different values of HLAT as specified in Table 10-22.
Table 10-22. Shift OF SSF and SSV from SADR
Document #: 38-02040 Rev. *F
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
Must be same in each of the eight
000
001
010
011
100
101
110
111
Will be same in each of the eight
Comparand Register (odd)
Comparand Register (even)
71
devices
devices
A
B
Figure 10-34. x144 Table with Eight Devices
Max Table Size
256K × 144 bits
992K × 144 bits
32K × 144 bits
0
Location
address
262142
GMR
L
0
2
4
6
K
CFG = 0101010101010101
143
143
Note
(144-bit configuration)
Even
A
. During 144-bit searches of 144-bit-configured tables, the
Number of CLK Cycles
Odd
B
0
1
2
3
4
5
6
7
0
0
Latency in CLK Cycles
(First matching entry)
4
5
6
CYNSE70128
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