CYNSE70128-83BGI Cypress Semiconductor Corp, CYNSE70128-83BGI Datasheet - Page 105

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CYNSE70128-83BGI

Manufacturer Part Number
CYNSE70128-83BGI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYNSE70128-83BGI

Operating Supply Voltage (min)
1.425V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Package Type
BGA
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant

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Quantity
Price
Part Number:
CYNSE70128-83BGI
Manufacturer:
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Quantity:
46
12.0
Table 12-1 describes the commands used to generate addresses on the SRAM address bus. The index [15:0] field contains the
address of a 72-bit entry that results in a hit in 72-bit-configured quadrant. It is the address of the 72-bit entry that lies at the 144-bit
page, and the 288-bit page boundaries in 144-bit- and 288-bit-configured quadrants, respectively.
”Registers” on page 15 of this specification, describes the NFA and SSR registers. ADR[15:0] contains the address supplied on
the DQ bus during PIO access to the CYNSE70128. Command bits 8, 7, and 6 {CMD[8:6]} are passed from the command to the
SRAM address bus. See ”Commands” on page 21, for more information. ID[4:0] is the ID of the device driving the SRAM bus
(see ”Pinout Description” on page 130 for more information).
Document #: 38-02040 Rev. *F
SRAM Addressing
DQ[71:0]
Figure 11-3. FULL Generation in a Cascaded Table
FULO[1]
3
FULO[1]
3
3
2
FULI
FULI
FULI
FULO[1]
2
2
1
FULO[1]
1
1
0
0
0
CYNSE70128
CYNSE70128
CYNSE70128
CYNSE70128
CYNSE70128
CYNSE70128
CYNSE70128
CYNSE70128
FULO[0]
6
6
6
6
6
6
6
6
FULO[0]
5
5
5
5
5
5
5
5
FULO[0]
4
4
4
4
4
FULI
4
FULI
FULI
FULI
FULI
FULO[0]
FULI
4
4
FULO[1] FULO[0]
FULI
FULI
3
3
3
3
3
FULO[0]
2
2
2
2
FULO[0]
2
FULO[0]
1
1
1
1
1
0
0
0
0
0
FULL
FULL
FULL
FULL
FULL
FULL
FULL
CYNSE70128
V
V
FULL
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Page 105 of 137

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