CY7C166-15VC Cypress Semiconductor Corp, CY7C166-15VC Datasheet - Page 7

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CY7C166-15VC

Manufacturer Part Number
CY7C166-15VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C166-15VC

Density
64Kb
Access Time (max)
15ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
14b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
115mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
24
Word Size
4b
Number Of Words
16K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C166-15VC
Manufacturer:
CY
Quantity:
1 725
Part Number:
CY7C166-15VC
Manufacturer:
CY
Quantity:
1 481
Part Number:
CY7C166-15VC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Waveforms
Document #: 38-05025 Rev. *C
Write Cycle No. 1(WE Controlled)
ADDRESS
Write Cycle No. 2(CE Controlled)
Notes
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
12. CY7C166 only: Data I/O will be high-impedance if OE = V
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
DATA IN
DATA I/O
ADDRESS
DATA I/O
DATA IN
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
WE
CE
CE
WE
(continued)
t
SA
t
DATA UNDEFINED
SA
[11,12,13]
[11,12]
IH
.
t
SCE
t
t
AW
AW
t
t
WC
WC
DATA
t
SCE
t
PWE
t
HZWE
IN
VALID
t
DATA
PWE
t
SD
t
SD
IN
VALID
HIGH IMPEDANCE
HIGH IMPEDANCE
t
HD
t
HD
t
LZWE
t
HA
t
HA
CY7C166
Page 7 of 12
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