MT46V8M16P-75Z Micron Technology Inc, MT46V8M16P-75Z Datasheet - Page 7

• Manufacturer Part Number: MT46V8M16P-75Z
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V8M16P-75Z

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 140mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 4:
Figure 5:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
16 Meg x 8 Functional Block Diagram
8 Meg x 16 Functional Block Diagram
BA0, BA1
A0–A11,
CAS#
RAS#
WE#
CKE
CK#
CS#
CK
14
BA0, BA1
A0–A11,
ADDRESS
REGISTER
CAS#
RAS#
WE#
CKE
CK#
CS#
MODE REGISTERS
CK
CONTROL
LOGIC
14
14
ADDRESS
REGISTER
MODE REGISTERS
CONTROL
COUNTER
REFRESH
12
LOGIC
14
10
2
12
12
ADDRESS
2
ROW-
MUX
9
COUNTER
REFRESH
ADDRESS
2
2
ROW-
MUX
COUNTER/
12
CONTROL
COLUMN-
ADDRESS
LATCH
BANK
LOGIC
12
COUNTER/
CONTROL
COLUMN-
ADDRESS
LOGIC
LATCH
BANK
12
DECODER
ADDRESS
BANK0
LATCH
ROW-
&
9
1
DECODER
ADDRESS
BANK0
LATCH
ROW-
4096
&
7
8
1
4096
SENSE AMPLIFIERS
DM MASK LOGIC
(4,096 x 512 x 16)
I/O GATING
DECODER
MEMORY
COLUMN
BANK0
ARRAY
(x16)
8192
512
BANK1
SENSE AMPLIFIERS
DM MASK LOGIC
(4,096 x 256 x 32)
I/O GATING
COLUMN
DECODER
MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK0
ARRAY
BANK2
(x32)
8192
256
BANK1
BANK3
BANK2
16
BANK3
128Mb: x4, x8, x16 DDR SDRAM
32
16
16
32
LATCH
READ
32
Functional Block Diagrams
LATCH
READ
Out
CK
CK
Out
CK
CK
DRIVERS
DRIVERS
WRITE
WRITE
FIFO
FIFO
8
8
&
&
16
16
CK
In
CK
In
MUX
COL0
COL0
MASK
DATA
MUX
COL0
COL0
MASK
DATA
16
2
32
4
©2004 Micron Technology, Inc. All rights reserved.
1
1
8
8
GENERATOR
2
2
16
16
GENERATOR
REGISTERS
REGISTERS
DQS
INPUT
16
INPUT
DQS
8
DATA
1
1
8
8
2
2
16
16
DATA
2
1
1
8
2
16
DRVRS
DQS
1
DLL
DRVRS
DQS
CK
2
DLL
CK
RCVRS
RCVRS
DQ0–DQ15
LDQS
UDQS
LDM,
UDM
DQ0–DQ7
DQS
DM