MT46V8M16P-75Z Micron Technology Inc, MT46V8M16P-75Z Datasheet - Page 55

MT46V8M16P-75Z

Manufacturer Part Number
MT46V8M16P-75Z
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46V8M16P-75Z

Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
140mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46V8M16P-75Z:D
Manufacturer:
MICRON
Quantity:
2 790
Part Number:
MT46V8M16P-75Z:D
Manufacturer:
MICRON
Quantity:
20 000
Figure 28:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
Random READ Accesses
Notes:
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
DQS
DQS
DQS
CK#
CK#
CK#
1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
3. n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal
DQ
DQ
DQ
CK
CK
CK
Bank,
Col n
READ
READ
READ
Bank,
Bank,
Col n
Col n
T0
T0
T0
CL = 2
Bank,
Col x
Bank,
READ
READ
Bank,
READ
Col x
t
Col x
AC,
T1
T1
T1
CL = 2.5
t
DQSCK, and
CL = 3
55
T2
Bank,
READ
READ
Col b
READ
Bank,
Bank,
Col b
Col b
T2n
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DO
DQSQ.
n
T2n
T3
DO
DO
128Mb: x4, x8, x16 DDR SDRAM
n'
n
Bank,
Col g
Bank,
Bank,
READ
Col g
T3n
READ
READ
Col g
T3
T3
DON’T CARE
DO
DO
DO
n'
n
x
T3n
T3n
T4
DO
DO
n'
DO
x'
x
©2004 Micron Technology, Inc. All rights reserved.
T4n
T4
T4
NOP
NOP
NOP
DO
DO
DO
x
b
x'
TRANSITIONING DATA
T4n
T4n
T5
DO
x'
DO
DO
b'
b
Operations
T5n
T5
T5
NOP
NOP
NOP
DO
DO
DO
b'
b
g
T5n
T5n
DO
b'

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