MT4LC4M16F5TG-5 Micron Technology Inc, MT4LC4M16F5TG-5 Datasheet - Page 3

• Manufacturer Part Number: MT4LC4M16F5TG-5
• Manufacturer: Micron Technology Inc
• Type: FPMr

Specifications of MT4LC4M16F5TG-5

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 12b
• Access Time (max): 25ns
• Maximum Clock Rate: Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 105mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

DRAM REFRESH
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all rows in the
DRAM array at least once every 64ms. The recom-
mended procedure is to execute 4,096 CBR REFRESH
cycles, either uniformly spaced or grouped in bursts,
every 64ms. The MT4LC4M16F5 internally refreshes
one row for every CBR cycle, so executing 4,096 CBR
cycles covers all rows. The CBR REFRESH will invoke the
internal refresh counter for automatic RAS# address-
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
The supply voltage must be maintained at the speci-
LOWER BYTE
UPPER BYTE
(DQ8-DQ15)
(DQ0-DQ7)
OF WORD
OF WORD
CASH#
CASL#
RAS#
WE#
STORED
X = NOT EFFECTIVE (DON'T CARE)
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
WORD and BYTE WRITE Example
INPUT
DATA
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
ADDRESS 0
WORD WRITE
INPUT
DATA
1
0
1
0
1
1
1
1
Figure 1
STORED
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
3
STORED
DATA
ing. Alternatively, RAS#-ONLY REFRESH capability is
inherently provided. However, with this method some
compatibility issues may become apparent. JEDEC
strongly recommends the use of CBR REFRESH for this
device.
STANDBY
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
Returning RAS# and CAS# HIGH terminates a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LOWER BYTE WRITE
INPUT
DATA
ADDRESS 1
1
1
0
1
1
1
1
1
X
X
X
X
X
X
X
X
INPUT
DATA
STORED
DATA
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
4 MEG x 16
FPM DRAM
©2000, Micron Technology, Inc.
OBSOLETE