LH28F016SUT-10 Sharp Electronics, LH28F016SUT-10 Datasheet - Page 6

• Manufacturer Part Number: LH28F016SUT-10
• Manufacturer: Sharp Electronics

Specifications of LH28F016SUT-10

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

LH28F016SU
Registers to accomplish various functions:
•
•
•
Word-Wide modes are shown in Figures 5 and 6.
RY
tie many RY
figuration such as a Resident Flash Array.
enable function with two input pins, CE
pins have exactly the same functionality as the regular
chip-enable pin CE
chip designs, CE
as the chip enable input. The LH28F016SU uses the
logical combination of these two signals to enable or
disable the entire chip. Both CE
tive low to enable the device and if either one becomes
inactive, the chip will be disabled. This feature, along
with the open drain RY
signer to reduce the number of control pins used in a
large array of 16M devices.
the LH28F016SU. BY
with address A
byte. On the other hand, BY
16-bit operation with address A
order address and address A
A block diagram is shown in Figure 3.
access time of each version, as follows:
6
TEMPERATURE
The LH28F016SU contains three types of Status
A Compatible Status Register (CSR) which is 100%
compatible with the LH28F008SA Flash memory’s
Status Register. This register, when used alone, pro-
vides a straightforward upgrade capability to the
LH28F016SU from a LH28F008SA based design.
A Global Status Register (GSR) which informs the
system of command Queue status, Page Buffer sta-
tus, and overall Write State Machine (WSM) status.
32 Block Status Registers (BSRs) which provide
block-specific status information such as the block
lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
The LH28F016SU incorporates an open drain
The LH28F016SU also incorporates a dual chip-
The BY
The LH28F016SU is specified for a maximum
»
OPERATING
/ BY
0 - 70°C
0 - 70°C
0 - 70°C
0 - 70°C
»
output pin. This feature allows the user to OR-
»
T E
»
/ BY
»
pin allows either x8 or x16 read/writes to
0
»
pins together in a multiple memory con-
»
selecting between low byte and high
1
may be tied to ground and use CE
»
on the LH28F008SA. For minimum
V
4.75 - 5.25 V
»
T E
4.5 - 5.5 V
3.0 - 3.6 V
2.7 - 3.6 V
CC
»
/ BY
»
at logic low selects 8-bit mode
SUPPLY
»
pin, allows the 0system de-
»
T E
0
is not used (don’t care).
»
0
1
»
at logic high enables
and CE
becoming the lowest
»
0
MAX. ACCESS
and CE
»
1
120 ns
160 ns
(T
must be ac-
80 ns
70 ns
ACC
»
1
. These
)
»
0
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
(1 mA at 3.3 V).
when the RP
transitions low, any current operation is aborted and the
device is put into the deep power-down mode. This mode
brings the device power consumption to less than 5 µA
typically, and provides additional write protection by
acting as a device reset pin during power transitions.
When the power is turned on, RP
der to return the device to default configuration. When
the 3/5
occured, or at the power on/off, RP
low in order to protect data from noise. A recovery time
of 550 ns (V
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR regis-
ters are cleared.
either CE
with all input control pins at CMOS levels. In this mode,
the device typically draws an I
10 µA.
The LH28F016SU incorporates an Automatic Power
In APS mode, the typical I
A Deep Power-Down mode of operation is invoked
A CMOS Standby mode of operation is enabled when
»
pin is switched, or when the power transition is
»
0
or CE
CC
»
(called PWD on the LH28F008SA) pin
16M (1M × 16, 2M × 8) Flash Memory
= 5.0 V ± 0.5 V) is required from RP
»
1
transitions high and RP
CC
current is 2 mA at 5.0 V
CC
»
pin turned to low or-
standby current of
»
is required to stay
»
stays high
»