LH28F016SUT-10 Sharp Electronics, LH28F016SUT-10 Datasheet - Page 5

• Manufacturer Part Number: LH28F016SUT-10
• Manufacturer: Sharp Electronics

Specifications of LH28F016SUT-10

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

16M (1M × 16, 2M × 8) Flash Memory
PIN DESCRIPTION (Continued)
tem interface between the microprocessor or
microcontroller and the internal memory operation.
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the LH28F008SA 8M Flash memory.
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
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word increments typically within 8 µs, a 25% improve-
ment over the LH28F008SA. A Block Erase operation
erases one of the 32 blocks in typically 0.7 seconds,
independent of the other blocks, which is about 55%
improvement over the LH28F008SA.
SYMBOL
A Command User Interface (CUI) serves as the sys-
Internal Algorithm Automation allows Byte/Word
A Superset of commands have been added to the
Page Buffer Writes to Flash
Command Queuing Capability
Automatic Data Writes During Erase
Software Locking of Memory Blocks
Two-Byte Successive Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
BYTE
GND
V
V
WP
3/5
NC
PP
CC
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INPUT
INPUT
INPUT
SUPPLY
SUPPLY
SUPPLY
TYPE
WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP is low, those locked blocks as reflected by the Block-Lock Status
bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high,
all blocks can be Written or Erased regardless of the state of the lock-bits. The WP
input buffer is disabled when RP
BYTE ENABLE: BYTE low places device x8 mode. All data is then input or output
on DQ
byte. BYTE high places the device in x16 mode, and turns off the A
Address A
3.3/5.0 VOLT SELECT: 3/5
low configures internal circuits for 5.0 V operation.
NOTES: Reading the array with 3/5
device. There is a significant delay from 3/5
ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing
words/bytes/pages into the flash array.
DEVICE POWER SUPPLY (3.3 V ±0.3 V, 5.0 V ±0.5 V) (2.7 V ~ 3.6 V at Read
Operation) : Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
NO CONNECT: No internal connection to die, lead may be driven or left floating.
0
- DQ
1
, then becomes the lowest order address.
7
, and DQ
8
- DQ
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high configures internal circuits for 3.3 V operation. 3/5
256 Bytes (128 Words) each to allow page data writes.
This feature can improve a system write performance
over previous flash memory devices.
commands to the device. Three Status Registers
(described in detail later) and a RY
provide information on the progress of the requested
operation.
plete before the next operation can be requested, the
LH28F016SU allows queuing of the next operation while
the memory executes the current operation. This elimi-
nates system overhead when writing several bytes in a
row to the array or erasing several blocks at the same
time. The LH2F016SUR-10 can also perform write op-
erations to one block of memory while performing erase
of another block.
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F016SU has a master Write
Protect pin (WP
memory blocks whose lock-bits are set.
15
NAME AND FUNCTION
The LH28F016SU incorporates two Page Buffers of
All operations are started by a sequence of Write
While the LH28F008SA requires an operation to com-
The LH28F016SU provides user-selectable block
float. Address A
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transitions low (deep power-down mode).
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high in a 5.0 V system could damage the
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switching to valid data.
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) which prevents any modifications to
0
selects between the high and low
0
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input buffer.
/ BY
LH28F016SU
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output pin
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