LM98714BCMT National Semiconductor, LM98714BCMT Datasheet - Page 5

• Manufacturer Part Number: LM98714BCMT
• Manufacturer: National Semiconductor

Specifications of LM98714BCMT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Pin Descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pin
CLK3
CLK2
CLK1
SH
RESET
SH_R
SDIO
SCLK
SEN
AGND
V
VREFB
VREFT
V
AGND
VCLP
V
AGND
OS
AGND
OS
AGND
OS
AGND
DGND
V
DVB
INCLK+
INCLK-
DOUT7/
TXCLK+
DOUT6/
TXCLK-
DOUT5/
TXOUT2+
DOUT4/
TXOUT2-
DOUT3/
TXOUT1+
DOUT2/
TXOUT1-
A
A
A
R
R
G
B
Name
O
O
O
O
I
I
I/O
I
I
O
O
IO
I
I
I
O
I
I
O
O
O
O
O
O
I/O
D
D
D
D
D
D
D
D
D
P
P
A
A
P
P
A
P
P
A
P
A
P
A
P
P
P
P
D
D
D
D
D
D
D
D
Typ
PU
PD
PU
PD
PU
PD
PD
PU
Res
Configurable sensor control output.
Configurable sensor control output.
Configurable sensor control output.
Sensor - Shift or transfer control signal for CCD and CIS sensors.
Active-low master reset. NC when function not being used.
External request for an SH pulse.
Serial Interface Data Input
Serial Interface shift register clock.
Active-low chip enable for the Serial Interface.
Analog ground return.
Analog power supply. Bypass voltage source with 4.7µF and pin with 0.1µF to
AGND.
Bottom of ADC reference. Bypass with a 0.1µF capacitor to ground.
Top of ADC reference. Bypass with a 0.1µF capacitor to ground.
Analog power supply. Bypass voltage source with 4.7µF and pin with 0.1µF to
AGND.
Analog ground return.
Input Clamp Voltage. Normally bypassed with a 0.1µF, and a 4.7µF capacitor to
AGND. An external reference voltage may be applied to this pin.
Analog power supply. Bypass voltage source with 4.7µF and pin with 0.1µF to
AGND.
Analog ground return.
Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.
Analog ground return.
Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.
Analog ground return.
Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.
Analog ground return.
Digital ground return.
Power supply input for internal voltage reference generator. Bypass this supply
pin with a 0.1µF capacitor.
Digital Core Voltage bypass. Not an input. Bypass with 0.1µF capacitor to
DGND.
Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS
clock is selected when pin 29 is held at DGND, otherwise clock is configured
for LVDS operation.
Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in
LVDS Mode.
Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in
LVDS Mode.
Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS
Mode.
Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS
Mode.
Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS
Mode.
Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS
Mode.
5
Description
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