MT4LSDT1664HY-133D1 Micron Technology Inc, MT4LSDT1664HY-133D1 Datasheet - Page 4

• Manufacturer Part Number: MT4LSDT1664HY-133D1
• Description: MODULE SDRAM 128MB 144SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT4LSDT1664HY-133D1

• Memory Type: SDRAM
• Memory Size: 128MB
• Speed: 133MHz
• Features: -
• Package / Case: 144-SODIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 5:
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
142, 144, 149–151, 153–
28, 29, 46, 47, 112, 113,
97–101, 103–104, 139–
33–38, 117–121, 123,
74–77, 86–89, 91–95,
Pin Numbers
156, 158–161
126 (128MB)
27, 111, 115
130, 131
165–167
39, 122
42, 79
30, 45
128
83
82
Pin Descriptions
Pins may not correlate with symbols; refer to Table 4 on page 3 for more information
(32MB, 64MB)
RAS#, CAS#,
DQ0–DQ63
BA0, BA1
CK0, CK2
DQMB0–
SA0–SA2
Symbol
S0#, S2#
(128MB)
DQMB7
A0–A11
A0–A12
CKE0
WE#
SDA
SCL
Input/Output
Input/Output
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Command inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW)
the CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in progress).
CKE is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including
CK, are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial clock for presence-detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to
configure the presence-detect device.
Serial presence-detect data: SDA is a bidirectional pin used
to transfer addresses and data into and out of the presence-
detect portion of the module.
Data I/Os: Data bus.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
Description
©2002 Micron Technology, Inc. All rights reserved.